公开(公告)号：US20220391110A1

公开(公告)日：2022-12-08

申请号：US17865594

申请日：2022-07-15

Applicant: Intel Corporation

Inventor： Fei Wang ,  John Browne ,  Laurent Coquerel

IPC: G06F3/06

Abstract: An accelerator device may access an input data chunk to be compressed by the accelerator device. The accelerator device may access an entropy value for the input data chunk. The accelerator device may compress the input data chunk or return an indication that the input data chunk will not be compressed based on the entropy value and an entropy threshold.

公开(公告)号：US09787332B2

公开(公告)日：2017-10-10

申请号：US14854647

申请日：2015-09-15

Applicant: Intel Corporation

Inventor： James D. Guilford ,  Vinodh Gopal ,  Laurent Coquerel

IPC: H04L1/00 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/6312 ,  G06F11/1076 ,  H03M7/3086 ,  H03M7/4037 ,  H03M7/6041

Abstract: A compression engine may be designed for more efficient error checking of a compressed stream, to include adaptation of a heterogeneous design that includes interleaved hardware and software stages of compression and decompression. An output of a string matcher may be reversed to generate a bit stream, which is then compared with an input stream to the compression engine as a first error check. A final compressed output of the compression engine may be partially decompressed to reverse entropy code encoding of an entropy code encoder. The partially decompressed output may be compared with an output of an entropy code generator to perform a second error check. Finding an error at the first error check greatly reduces the latency of generating a fault or exception, as does performing computing-intensive aspects of the compression and decompression with software instead of specialized hardware.

公开(公告)号：US20170077964A1

公开(公告)日：2017-03-16

申请号：US14854647

申请日：2015-09-15

Applicant: Intel Corporation

Inventor： James D. Guilford ,  Vinodh Gopal ,  Laurent Coquerel

IPC: H03M13/00 ,  G06F11/10

CPC classification number: H03M13/6312 ,  G06F11/1076 ,  H03M7/3086 ,  H03M7/4037 ,  H03M7/6041

Abstract: A compression engine may be designed for more efficient error checking of a compressed stream, to include adaptation of a heterogeneous design that includes interleaved hardware and software stages of compression and decompression. An output of a string matcher may be reversed to generate a bit stream, which is then compared with an input stream to the compression engine as a first error check. A final compressed output of the compression engine may be partially decompressed to reverse entropy code encoding of an entropy code encoder. The partially decompressed output may be compared with an output of an entropy code generator to perform a second error check. Finding an error at the first error check greatly reduces the latency of generating a fault or exception, as does performing computing-intensive aspects of the compression and decompression with software instead of specialized hardware.

Abstract translation: 可以设计压缩引擎用于对压缩流进行更有效的错误检查，以包括包括交织的硬件和压缩和解压缩的软件阶段的异构设计的适应。 字符串匹配器的输出可以被反转以产生位流，然后将其与作为第一错误检查的压缩引擎的输入流进行比较。 压缩引擎的最终压缩输出可以被部分解压缩以反转熵码编码器的熵码编码。 可以将部分解压缩的输出与熵码发生器的输出进行比较以执行第二错误检查。 在第一个错误检查中查找错误大大减少了生成故障或异常的延迟，同时执行使用软件而不是专用硬件进行压缩和解压缩的计算密集型方面。

公开(公告)号：US20230418773A1

公开(公告)日：2023-12-28

申请号：US18035705

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Xin Zeng ,  Ned Smith ,  Weigang Li ,  Junyuan Wang ,  Songwu Shen ,  Zijuan Fan ,  Yao Huo ,  Maksim Lukoshkov ,  Laurent Coquerel

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based on a message from the IOM MU (120) which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device (118) performs a search, based on a DMA request, to determine if any registry (330) entry (332) indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU (120) is contingent on a result of the search.

公开(公告)号：US20190042354A1

公开(公告)日：2019-02-07

申请号：US16024771

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Laurent Coquerel ,  Paul Hough

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  G06F3/06 ,  H03M7/30

Abstract: Technologies for error recovery in compressed data streams include a compute device configured to compress uncompressed data of an input stream to generate compressed data, perform a compression error check on the compressed data to verify integrity of the compressed data, and determine, as a result of the performed compression error check, whether the compressed data included a compression error. The compute device is further configured to transfer, in response to a determination that the performed compression error check indicated that the compressed data included the compression error, the uncompressed data into a destination buffer, and store an indication with the uncompressed data into the destination buffer, wherein the indication is usable to identify that the uncompressed data has been transferred into the destination buffer. Other embodiments are described herein.

公开(公告)号：US12271327B2

公开(公告)日：2025-04-08

申请号：US18035705

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Xin Zeng ,  Ned Smith ,  Weigang Li ,  Junyuan Wang ,  Songwu Shen ,  Zijuan Fan ,  Yao Huo ,  Maksim Lukoshkov ,  Laurent Coquerel

IPC: G06F13/28

Abstract: Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based on a message from the IOM MU (120) which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device (118) performs a search, based on a DMA request, to determine if any registry (330) entry (332) indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU (120) is contingent on a result of the search.

公开(公告)号：US20250110903A1

公开(公告)日：2025-04-03

申请号：US18978180

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Dongsheng Liang ,  Junyuan Wang ,  Xiaoyan Bo ,  Yuze Xiao ,  Haoxiang Sun ,  Weigang Li ,  Marian Horgan ,  Fei Wang ,  John J. Browne ,  Laurent Coquerel ,  Giovanni Cabiddu ,  Vijay Sundar Selvamani ,  Steven Linsell ,  Karthikeyan Gopal ,  Deepika Ranganatha

IPC: G06F13/28

Abstract: A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.

公开(公告)号：US20230350720A1

公开(公告)日：2023-11-02

申请号：US18221057

申请日：2023-07-12

Applicant: Intel Corporation

Inventor： Marian Horgan ,  Laurent Coquerel ,  John Browne

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/4881

Abstract: An accelerator device may receive, from an application, an application programming interface (API) call to chain an encryption operation for data and a data transformation operation for the data. The accelerator device may cause two or more hardware accelerators of the accelerator device to execute the encryption operation for the data and the data transformation operation for the data based on the API call.

公开(公告)号：US20230342206A1

公开(公告)日：2023-10-26

申请号：US18214830

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Laurent Coquerel ,  Fei Wang ,  Smita Kumar ,  Phani Krishna Sagiraju ,  John J. Browne

IPC: G06F9/50 ,  H03M7/30

CPC classification number: G06F9/5027 ,  H03M7/30

Abstract: An accelerator or system including an accelerator can include an input interface to receive input data to be compressed and user application parameters for invocation of compression. The accelerator can include circuitry to identify a compression algorithm from configuration data provided with the input data. The user application parameters may not include parameters specifying entropy thresholds for compression of the input data. The circuitry can generate headers specific to the compression algorithm. The circuitry can generate uncompressed data blocks comprising blocks of the input data and corresponding headers. The circuitry can determine whether to provide the uncompressed data blocks or compressed data blocks based at least in part on entropy of the input data. Other methods, systems, and apparatuses are described.

公开(公告)号：US20220368348A1

公开(公告)日：2022-11-17

申请号：US17870659

申请日：2022-07-21

Applicant: INTEL CORPORATION

Inventor： Laurent Coquerel ,  Fei Wang ,  John Browne ,  Smita Kumar ,  Declan Doherty ,  Marlow Weston ,  Reshma Pattan

IPC: H03M7/30

Abstract: An accelerator device determines a compression format based on a header of a structured data element to be decompressed. The accelerator device may configure the accelerator device based on the compression format. The accelerator device may decompress a data block of the structured data element based on the configuration.