公开(公告)号：US20220368348A1

公开(公告)日：2022-11-17

申请号：US17870659

申请日：2022-07-21

Applicant: INTEL CORPORATION

Inventor： Laurent Coquerel ,  Fei Wang ,  John Browne ,  Smita Kumar ,  Declan Doherty ,  Marlow Weston ,  Reshma Pattan

IPC: H03M7/30

Abstract: An accelerator device determines a compression format based on a header of a structured data element to be decompressed. The accelerator device may configure the accelerator device based on the compression format. The accelerator device may decompress a data block of the structured data element based on the configuration.

公开(公告)号：US10932202B2

公开(公告)日：2021-02-23

申请号：US16442094

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Harry van Haaren ,  Reshma Pattan ,  Radu Nicolau

IPC: G06F13/28 ,  G06F9/54 ,  H04L12/861 ,  H04W28/00 ,  H04W52/24 ,  H04W24/10 ,  H04B17/336 ,  H04W72/04 ,  H04L1/00 ,  H04L12/883 ,  H04W52/36 ,  H04W52/42 ,  H04B7/0413

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

公开(公告)号：US11431565B2

公开(公告)日：2022-08-30

申请号：US16160176

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Mohammad Abdul Awal ,  Jasvinder Singh ,  Reshma Pattan ,  David Hunt ,  Declan Doherty ,  Chris Macnamara

IPC: H04L41/0816 ,  H04L49/90 ,  H04L43/16 ,  H04L43/0894 ,  H04L49/00 ,  H04L43/10

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

公开(公告)号：US20250013507A1

公开(公告)日：2025-01-09

申请号：US18891976

申请日：2024-09-20

Applicant: Intel Corporation

Inventor： Chris M. MacNamara ,  John J. Browne ,  Przemyslaw J. Perycz ,  Pawel S. Zak ,  Reshma Pattan

IPC: G06F9/50 ,  G06F1/26 ,  G06F9/48

Abstract: Techniques for computer power management are disclosed. In one embodiment, a data center includes several compute nodes and a power management node. Power telemetry data is gathered at each of the compute nodes and sent to the power management node. The power management node analyzes the telemetry data, such as by applying filtering to identify certain metrics. The power management node may use rules to analyze the telemetry data and determine whether power management actions should be performed. The power management node may instruct the compute node to, e.g., change a power state of a processor or processor core. In some embodiments, cores may be managed by an orchestrator, and the orchestrator may identify cores to be placed in high-power and low-power states, as appropriate.

公开(公告)号：US20190294570A1

公开(公告)日：2019-09-26

申请号：US16442094

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Harry van Haaren ,  Reshma Pattan ,  Radu Nicolau

IPC: G06F13/28 ,  G06F9/54 ,  H04L12/883

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.