公开(公告)号：US10707121B2

公开(公告)日：2020-07-07

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Mark A. Levan ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao

IPC: H01L21/768 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：US20250110903A1

公开(公告)日：2025-04-03

申请号：US18978180

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Dongsheng Liang ,  Junyuan Wang ,  Xiaoyan Bo ,  Yuze Xiao ,  Haoxiang Sun ,  Weigang Li ,  Marian Horgan ,  Fei Wang ,  John J. Browne ,  Laurent Coquerel ,  Giovanni Cabiddu ,  Vijay Sundar Selvamani ,  Steven Linsell ,  Karthikeyan Gopal ,  Deepika Ranganatha

IPC: G06F13/28

Abstract: A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.

公开(公告)号：US20230342206A1

公开(公告)日：2023-10-26

申请号：US18214830

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Laurent Coquerel ,  Fei Wang ,  Smita Kumar ,  Phani Krishna Sagiraju ,  John J. Browne

IPC: G06F9/50 ,  H03M7/30

CPC classification number: G06F9/5027 ,  H03M7/30

Abstract: An accelerator or system including an accelerator can include an input interface to receive input data to be compressed and user application parameters for invocation of compression. The accelerator can include circuitry to identify a compression algorithm from configuration data provided with the input data. The user application parameters may not include parameters specifying entropy thresholds for compression of the input data. The circuitry can generate headers specific to the compression algorithm. The circuitry can generate uncompressed data blocks comprising blocks of the input data and corresponding headers. The circuitry can determine whether to provide the uncompressed data blocks or compressed data blocks based at least in part on entropy of the input data. Other methods, systems, and apparatuses are described.

公开(公告)号：US20220415908A1

公开(公告)日：2022-12-29

申请号：US17375540

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Guangyu Huang ,  Dipanjan Basu ,  Meng-Wei Kuo ,  Randy Koval ,  Henok Mebrahtu ,  Minsheng Wang ,  Jie Li ,  Fei Wang ,  Qun Gao ,  Xingui Zhang ,  Guanjie Li

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

公开(公告)号：US20220368348A1

公开(公告)日：2022-11-17

申请号：US17870659

申请日：2022-07-21

Applicant: INTEL CORPORATION

Inventor： Laurent Coquerel ,  Fei Wang ,  John Browne ,  Smita Kumar ,  Declan Doherty ,  Marlow Weston ,  Reshma Pattan

IPC: H03M7/30

Abstract: An accelerator device determines a compression format based on a header of a structured data element to be decompressed. The accelerator device may configure the accelerator device based on the compression format. The accelerator device may decompress a data block of the structured data element based on the configuration.

公开(公告)号：US20220391110A1

公开(公告)日：2022-12-08

申请号：US17865594

申请日：2022-07-15

Applicant: Intel Corporation

Inventor： Fei Wang ,  John Browne ,  Laurent Coquerel

IPC: G06F3/06

Abstract: An accelerator device may access an input data chunk to be compressed by the accelerator device. The accelerator device may access an entropy value for the input data chunk. The accelerator device may compress the input data chunk or return an indication that the input data chunk will not be compressed based on the entropy value and an entropy threshold.

公开(公告)号：US20180190540A1

公开(公告)日：2018-07-05

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao ,  Mark A. Levan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.