公开(公告)号：US09910484B2

公开(公告)日：2018-03-06

申请号：US14091125

申请日：2013-11-26

Applicant: INTEL CORPORATION

Inventor： Harry Muljono ,  Linda K. Sun

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  Y02D10/172

Abstract: Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.

公开(公告)号：US20150276857A1

公开(公告)日：2015-10-01

申请号：US14741346

申请日：2015-06-16

Applicant: INTEL CORPORATION

Inventor： Linda K. Sun ,  Harry Muljono

IPC: G01R31/28 ,  G01N27/22

CPC classification number: G01R31/2853 ,  G01N27/228 ,  G01R31/2884 ,  H01L22/34

Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.

Abstract translation: 焊盘电容测试电路可以耦合到诸如处理器的电子电路的一个或多个焊盘。 焊盘电容测试电路可以位于包括电子电路的管芯上。 焊盘电容测试电路可以将一个或多个焊盘的焊盘电压重置为零，然后通过上拉电阻将焊盘耦合到电源电压一段时间。 可以测量在该时间段结束时或之后的最后的焊盘电压。 焊盘电容可以根据最终焊盘电压的测量值和上拉电阻器的电源电压，时间周期和电阻的已知值来确定。

公开(公告)号：US10812075B2

公开(公告)日：2020-10-20

申请号：US16417511

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

IPC: H03K19/00 ,  H03K19/0175 ,  G06F13/40 ,  H04L25/02

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

公开(公告)号：US10944256B2

公开(公告)日：2021-03-09

申请号：US15939807

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Horaira Abu ,  Linda K. Sun

IPC: H02H9/04 ,  H01L27/02

Abstract: Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node. The additional voltage has a negative voltage value. The additional node is coupled to a gate of at least one transistor of the first circuit.

公开(公告)号：US20190280691A1

公开(公告)日：2019-09-12

申请号：US16417511

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

IPC: H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  G06F13/40

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

公开(公告)号：US10324124B2

公开(公告)日：2019-06-18

申请号：US14741346

申请日：2015-06-16

Applicant: INTEL CORPORATION

Inventor： Linda K. Sun ,  Harry Muljono

IPC: G01N27/22 ,  G01R31/28 ,  H01L21/66

Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.