公开(公告)号：US09940238B2

公开(公告)日：2018-04-10

申请号：US15602603

申请日：2017-05-23

Applicant: INTEL CORPORATION

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

IPC: G06F12/08 ,  G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.

公开(公告)号：US09690706B2

公开(公告)日：2017-06-27

申请号：US14668831

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

IPC: G06F12/08 ,  G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

Abstract: Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.

公开(公告)号：US20170255553A1

公开(公告)日：2017-09-07

申请号：US15602603

申请日：2017-05-23

Applicant: INTEL CORPORATION

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.

公开(公告)号：US09298629B2

公开(公告)日：2016-03-29

申请号：US14549874

申请日：2014-11-21

Applicant: INTEL CORPORATION

Inventor： Sailesh Kottapalli ,  Henk G. Neefs ,  Rahul Pal ,  Manoj K. Arora ,  Dheemanth Nagaraj

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/42

CPC classification number: G06F12/0833 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/4265 ,  G06F2212/621 ,  G06F2212/622

Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器 关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。 描述和要求保护其他实施例。

公开(公告)号：US08918592B2

公开(公告)日：2014-12-23

申请号：US14142044

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Sailesh Kottapalli ,  Henk G. Neefs ,  Rahul Pal ,  Manoj K. Arora ,  Dheemanth Nagaraj

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0833 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/4265 ,  G06F2212/621 ,  G06F2212/622

Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器 关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。 描述和要求保护其他实施例。