公开(公告)号：US09734054B1

公开(公告)日：2017-08-15

申请号：US15162480

申请日：2016-05-23

Applicant: Intel Corporation

Inventor： Massimo Sutera

IPC: G06F12/06 ,  G11C8/04 ,  G11C5/14 ,  G11C8/18 ,  G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/063 ,  G06F15/7821 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C8/04 ,  G11C8/06

Abstract: Methods and apparatus related to efficient implementation of geometric series are discussed herein. For example, memory stores data corresponding to a geometric series. Logic, coupled to the memory, generates a channel address based at least in part on a summation of a tag address and one or more geometric series components of the geometric series. Other embodiments are also claimed.

公开(公告)号：US10162750B2

公开(公告)日：2018-12-25

申请号：US14973397

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Massimo Sutera

IPC: G06F12/12 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/06 ,  G06T1/60 ,  G09G5/39

Abstract: System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address translated from the system address. The system address reconstruction logic includes logic configured to reconstruct one or more systems address fields as a function of the channel address, the number of memory controller target ways of the memory being equal to three, the number of bits of the granularity of interleaving of data among the memory controller target ways, the number of channels per memory controller target way, and the number of bits of the granularity of interleaving of data among the channels of a memory controller target way. Other aspects are described herein.

公开(公告)号：US10007606B2

公开(公告)日：2018-06-26

申请号：US15085599

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Brian S. Morris ,  Binata Bhattacharyya ,  Massimo Sutera

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F2212/283 ,  G06F2212/621

Abstract: Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.

公开(公告)号：US20170185315A1

公开(公告)日：2017-06-29

申请号：US14757926

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US10042562B2

公开(公告)日：2018-08-07

申请号：US15684936

申请日：2017-08-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0866 ,  G06F12/0893

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US09747041B2

公开(公告)日：2017-08-29

申请号：US14757926

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0866

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.