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    Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory
    9.
    发明授权
    Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory 有权
    本地缓存行的包含和非包容性跟踪，以避免缓存行内存上的近似存储器读取写入两级系统内存

    公开(公告)号：US09418009B2

    公开(公告)日：2016-08-16

    申请号：US14142045

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0888

    Abstract: A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.

    Abstract translation: 处理器可以包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理器可以包括逻辑电路，以使存储器控制器确定写入请求是远程生成还是本地生成，并且当写入请求被远程生成以指示存储器控制器在执行写入之前执行近似存储器的读取，当写入 请求在本地生成，并且由写入请求所针对的高速缓存行处于包含状态，以指示存储器控制器执行写入而不执行近似存储器的读取，并且当本地生成写入请求时， 写请求处于非包容状态，以指示存储器控制器在执行写操作之前读取存储器。

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