公开(公告)号：US20220262684A1

公开(公告)日：2022-08-18

申请号：US17738968

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20230360973A1

公开(公告)日：2023-11-09

申请号：US18223981

申请日：2023-07-19

Applicant: Intel Corporation

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00

CPC classification number: H01L21/823437 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/42372 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4238 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L21/845

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20210028066A1

公开(公告)日：2021-01-28

申请号：US17069265

申请日：2020-10-13

Applicant: INTEL CORPORATION

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240413016A1

公开(公告)日：2024-12-12

申请号：US18807193

申请日：2024-08-16

Applicant: Intel Corporation

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  G06F30/39 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.