公开(公告)号：US20240413016A1

公开(公告)日：2024-12-12

申请号：US18807193

申请日：2024-08-16

Applicant: Intel Corporation

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  G06F30/39 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20230360973A1

公开(公告)日：2023-11-09

申请号：US18223981

申请日：2023-07-19

Applicant: Intel Corporation

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00

CPC classification number: H01L21/823437 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/42372 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4238 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L21/845

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20220077302A1

公开(公告)日：2022-03-10

申请号：US17526986

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US20210028066A1

公开(公告)日：2021-01-28

申请号：US17069265

申请日：2020-10-13

Applicant: INTEL CORPORATION

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20190305112A1

公开(公告)日：2019-10-03

申请号：US15943556

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/088

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US20190305111A1

公开(公告)日：2019-10-03

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Christopher KENYON ,  Sridhar GOVINDARAJU ,  Chia-Hong JAN ,  Mark LIU ,  Szuya S. LIAO ,  Walid M. HAFEZ

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

公开(公告)号：US20220262684A1

公开(公告)日：2022-08-18

申请号：US17738968

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Sridhar GOVINDARAJU ,  Matthew J. PRINCE

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20220077145A1

公开(公告)日：2022-03-10

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20200286891A1

公开(公告)日：2020-09-10

申请号：US16294380

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Kiran CHIKKADI

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00 ,  H01L23/528

Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.

公开(公告)号：US20190304971A1

公开(公告)日：2019-10-03

申请号：US15941647

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.