公开(公告)号：US11200055B2

公开(公告)日：2021-12-14

申请号：US16474507

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Mark J. Charney ,  Barukh Ziv ,  Alexander Heinecke ,  Milind Girkar ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

公开(公告)号：US20200382303A1

公开(公告)日：2020-12-03

申请号：US16998913

申请日：2020-08-20

Applicant: Intel Corporation

Inventor： Milind Girkar ,  Jason W. Brandt ,  Michael LeMay

IPC: H04L9/32 ,  H04L9/08 ,  G06F21/60

Abstract: A processor core that includes a token generator circuit is to execute a first instruction in response to initialization of a software program that requests access to protected data output by a cryptographic operation. To execute the first instruction, the processor core is to: retrieve a key that is to be used by the cryptographic operation; trigger the token generator circuit to generate an authorization token; cryptographically encode the key and the authorization token within a key handle; store the key handle in memory; and embed the authorization token within a cryptographic instruction that is to perform the cryptographic operation. The cryptographic instruction may be associated with a first logical compartment of the software program that is authorized access to the protected data.

公开(公告)号：US20200007332A1

公开(公告)日：2020-01-02

申请号：US16024259

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Milind Girkar ,  Jason W. Brandt ,  Michael LeMay

IPC: H04L9/32 ,  G06F21/60 ,  H04L9/08

Abstract: A processor core that includes a token generator circuit is to execute a first instruction in response to initialization of a software program that requests access to protected data output by a cryptographic operation. To execute the first instruction, the processor core is to: retrieve a key that is to be used by the cryptographic operation; trigger the token generator circuit to generate an authorization token; cryptographically encode the key and the authorization token within a key handle; store the key handle in memory; and embed the authorization token within a cryptographic instruction that is to perform the cryptographic operation. The cryptographic instruction may be associated with a first logical compartment of the software program that is authorized access to the protected data.

公开(公告)号：US10459858B2

公开(公告)日：2019-10-29

申请号：US15804939

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John P. Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry H. Wang ,  Piyush N. Desai

IPC: G06F9/38 ,  G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34 ,  G06F11/30 ,  G06F12/0875

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US11036499B2

公开(公告)日：2021-06-15

申请号：US16613537

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Venkateswara R. Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Mark J. Charney ,  Carl Murray ,  Milind Girkar ,  Bret Toll

IPC: G06F9/30 ,  G06F7/548

Abstract: Embodiments of systems, apparatuses, and methods for performing controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

公开(公告)号：US11023231B2

公开(公告)日：2021-06-01

申请号：US15283384

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Roman S. Dubtsov ,  Robert Valentine ,  Jesus Corbal ,  Milind Girkar ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/302 ,  G06F9/30

Abstract: Disclosed embodiments relate to executing a vector-complex fused multiply-add Instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers identifies a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, generate a complex result by using the four products according to the instruction, and store a result to the corresponding position of the identified destination operand.

公开(公告)号：US10785028B2

公开(公告)日：2020-09-22

申请号：US16024259

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Milind Girkar ,  Jason W. Brandt ,  Michael LeMay

IPC: G06F21/00 ,  H04L9/32 ,  H04L9/08 ,  G06F21/60

Abstract: A processor core that includes a token generator circuit is to execute a first instruction in response to initialization of a software program that requests access to protected data output by a cryptographic operation. To execute the first instruction, the processor core is to: retrieve a key that is to be used by the cryptographic operation; trigger the token generator circuit to generate an authorization token; cryptographically encode the key and the authorization token within a key handle; store the key handle in memory; and embed the authorization token within a cryptographic instruction that is to perform the cryptographic operation. The cryptographic instruction may be associated with a first logical compartment of the software program that is authorized access to the protected data.

公开(公告)号：US12260213B2

公开(公告)日：2025-03-25

申请号：US17548214

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Mark J. Charney ,  Barukh Ziv ,  Alexander Heinecke ,  Milind Girkar ,  Simon Rubanovich

IPC: G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

公开(公告)号：US11838418B2

公开(公告)日：2023-12-05

申请号：US16998913

申请日：2020-08-20

Applicant: Intel Corporation

Inventor： Milind Girkar ,  Jason W. Brandt ,  Michael LeMay

IPC: G06F21/00 ,  H04L9/32 ,  H04L9/08 ,  G06F21/60

CPC classification number: H04L9/3213 ,  G06F21/602 ,  H04L9/0861

Abstract: A processor core that includes a token generator circuit is to execute a first instruction in response to initialization of a software program that requests access to protected data output by a cryptographic operation. To execute the first instruction, the processor core is to: retrieve a key that is to be used by the cryptographic operation; trigger the token generator circuit to generate an authorization token; cryptographically encode the key and the authorization token within a key handle; store the key handle in memory; and embed the authorization token within a cryptographic instruction that is to perform the cryptographic operation. The cryptographic instruction may be associated with a first logical compartment of the software program that is authorized access to the protected data.

公开(公告)号：US20180095758A1

公开(公告)日：2018-04-05

申请号：US15283384

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Roman S. Dubtsov ,  Robert Valentine ,  Jesus Corbal ,  Milind Girkar ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001

Abstract: Disclosed embodiments relate to executing a vector-complex fused multiply-add Instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers is to identify a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, to generate a complex result by summing the four products according to the instruction, and to store a result to the corresponding position of the identified destination operand.