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公开(公告)号：US12217130B2
公开(公告)日：2025-02-04
申请号：US18231917
申请日：2023-08-09
Applicant: Intel Corporation
Inventor： Xiang Zou
Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.
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公开(公告)号：US11748651B2
公开(公告)日：2023-09-05
申请号：US17988994
申请日：2022-11-17
Applicant: Intel Corporation
Inventor： Xiang Zou
CPC classification number: G06N10/00 , G06F9/30043 , G06F9/30101
Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.
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公开(公告)号：US11681533B2
公开(公告)日：2023-06-20
申请号：US16443593
申请日：2019-06-17
Applicant: Intel Corporation
Inventor： Ron Gabor , Alaa Alameldeen , Abhishek Basak , Fangfei Liu , Francis McKeen , Joseph Nuzman , Carlos Rozas , Igor Yanover , Xiang Zou
IPC: G06F9/30 , G06F9/38 , G06F12/1027 , G06F21/57
CPC classification number: G06F9/3842 , G06F9/30043 , G06F9/30047 , G06F9/30101 , G06F9/30189 , G06F12/1027 , G06F21/57 , G06F2212/68 , G06F2221/034
Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.
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公开(公告)号：US20220206818A1
公开(公告)日：2022-06-30
申请号：US17134334
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Alaa Alameldeen , Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.
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公开(公告)号：US20200272474A1
公开(公告)日：2020-08-27
申请号：US16443593
申请日：2019-06-17
Applicant: Intel Corporation
Inventor： Ron Gabor , Alaa Alameldeen , Abhishek Basak , Fangfei Liu , Francis McKeen , Joseph Nuzman , Carlos Rozas , Igor Yanover , Xiang Zou
IPC: G06F9/38 , G06F9/30 , G06F12/1027 , G06F21/57
Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.
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Patent Agency Ranking
公开(公告)号：US10459858B2
公开(公告)日：2019-10-29
申请号：US15804939
申请日：2017-11-06
Applicant: INTEL CORPORATION
Inventor： Hong Wang , Per Hammarlund , Xiang Zou , John P. Shen , Xinmin Tian , Milind Girkar , Perry H. Wang , Piyush N. Desai
Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.
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公开(公告)号：US20160274910A1
公开(公告)日：2016-09-22
申请号：US15166469
申请日：2016-05-27
Applicant: Intel Corporation
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
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公开(公告)号：US20230315473A1
公开(公告)日：2023-10-05
申请号：US17712139
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： Muhammad Azeem , Rangeen Basu Roy Chowdhury , Xiang Zou , Malihe Ahmadi , Joju Joseph Zajo , Ariel Sabba , Ammon Christiansen , Polychronis Xekalakis , Eliyah Kilada
CPC classification number: G06F9/382 , G06F9/3873 , G06F9/30149
Abstract: Embodiments of apparatuses and methods for variable-length instruction steering to instruction decode clusters are disclosed. In an embodiment, an apparatus includes a decode cluster and chunk steering circuitry. The decode cluster includes multiple instruction decoders. The chunk steering circuitry is to break a sequence of instruction bytes into a plurality of chunks, create a slice from a one or more of the plurality of chunks based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks, wherein the slice has a variable size and includes a plurality of instructions, and steer the slice to the decode cluster.
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公开(公告)号：US11550977B2
公开(公告)日：2023-01-10
申请号：US16261113
申请日：2019-01-29
Applicant: Intel Corporation
Inventor： Sahar Daraeizadeh , Anne Matsuura , Xiang Zou , Sonika Johri
Abstract: Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.
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公开(公告)号：US11531922B2
公开(公告)日：2022-12-20
申请号：US16144887
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Xiang Zou
Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.
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