公开(公告)号：US10585667B2

公开(公告)日：2020-03-10

申请号：US15900030

申请日：2018-02-20

申请人： Intel Corporation

发明人： Edward Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/38

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US09952859B2

公开(公告)日：2018-04-24

申请号：US15088043

申请日：2016-03-31

申请人： Intel Corporation

发明人： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20160216971A1

公开(公告)日：2016-07-28

申请号：US15088043

申请日：2016-03-31

申请人： Intel Corporation

发明人： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US10459858B2

公开(公告)日：2019-10-29

申请号：US15804939

申请日：2017-11-06

申请人： INTEL CORPORATION

发明人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John P. Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry H. Wang ,  Piyush N. Desai

IPC分类号： G06F9/38 ,  G06F13/24 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34 ,  G06F11/30 ,  G06F12/0875

摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US20180321936A1

公开(公告)日：2018-11-08

申请号：US15943609

申请日：2018-04-02

申请人： Intel Corporation

发明人： Edward Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20180307484A1

公开(公告)日：2018-10-25

申请号：US15900030

申请日：2018-02-20

申请人： Intel Corporation

发明人： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US09785576B2

公开(公告)日：2017-10-10

申请号：US14227178

申请日：2014-03-27

申请人： Intel Corporation

发明人： Thiam Wah Loh ,  Per Hammarlund ,  Andreas Wasserbauer ,  Swee Chong Peter Kuan ,  Eckhard Delfs ,  Deepak A. Mathaikutty ,  Stephen J. Robinson ,  Gautham N. Chinya ,  Perry H. Wang ,  Chee Weng Tan ,  Hong Wang ,  Reza Fortas

IPC分类号： G06F12/14 ,  G11C29/52 ,  G06F21/57 ,  G11C7/10 ,  G06F21/10

CPC分类号： G06F12/1408 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/032 ,  Y02D10/13

摘要： Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

公开(公告)号：US09442721B2

公开(公告)日：2016-09-13

申请号：US13722481

申请日：2012-12-20

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Colins ,  James P. Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/54 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

摘要翻译： 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

公开(公告)号：US11010166B2

公开(公告)日：2021-05-18

申请号：US15087854

申请日：2016-03-31

申请人： Intel Corporation

发明人： Debabrata Mohapatra ,  Perry H. Wang ,  Xiang Zou ,  Sang Kyun Kim ,  Deepak A. Mathaikutty ,  Gautham N. Chinya

IPC分类号： G06F9/302 ,  G06F9/318 ,  G06F9/30

摘要： A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

公开(公告)号：US10534613B2

公开(公告)日：2020-01-14

申请号：US15581791

申请日：2017-04-28

申请人： Intel Corporation

发明人： Gokce Keskin ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Tsung-Han Lin ,  Perry H. Wang ,  Hong Wang

IPC分类号： G06F9/38 ,  G06N3/08

摘要： Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.