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公开(公告)号：US20180287842A1
公开(公告)日：2018-10-04
申请号：US15882156
申请日：2018-01-29
Applicant: Intel Corporation
Inventor： Bernard Arambepola , Parveen K. Shukla , Thushara Hewavithana , Sahan S. Gamage
CPC classification number: H04L27/2627 , G06F7/768 , G06F12/00 , H03M13/271 , H04L1/0071 , H04L27/2628 , H04L27/263 , H04L27/2634 , H05K999/99
Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.
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公开(公告)号：US10305714B2
公开(公告)日：2019-05-28
申请号：US15882156
申请日：2018-01-29
Applicant: Intel Corporation
Inventor： Bernard Arambepola , Parveen K. Shukla , Thushara Hewavithana , Sahan S. Gamage
Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.
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公开(公告)号：US09742610B2
公开(公告)日：2017-08-22
申请号：US15069312
申请日：2016-03-14
Applicant: Intel Corporation
Inventor： Bernard Arambepola , Parveen K. Shukla , Thushara Hewavithana
CPC classification number: H04L27/2646 , H04L5/0007 , H04L25/0218 , H04L25/022 , H04L25/0232 , H04L25/03343 , H04L27/2607 , H04L27/2613 , H04L27/2647 , H04L27/2665 , H04L27/2678
Abstract: One embodiment provides an apparatus. The apparatus includes an optimization module configured to determine a guard interval remainder based, at least in part on a comparison of an allowable microreflection interference level and an actual microreflection interference level; and a windowing module configured to window an OFDM (orthogonal frequency division multiplexed) symbol utilizing the guard interval remainder. The apparatus may further include a channel estimator module configured to determine a predicted channel frequency response based, at least in part, on a probing symbol; and a pre-equalizer module configured to pre-equalize the OFDM symbol based, at least in part, on the predicted channel frequency response.
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Patent Agency Ranking
公开(公告)号：US09954708B2
公开(公告)日：2018-04-24
申请号：US14081586
申请日：2013-11-15
Applicant: Intel Corporation
Inventor： Bernard Arambepola , Parveen K. Shukla , Thushara Hewavithana , Sahan S. Gamage
CPC classification number: H04L27/2627 , G06F7/768 , G06F12/00 , H03M13/271 , H04L1/0071 , H04L27/2628 , H04L27/263 , H04L27/2634
Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.
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5.发明授权公开(公告)号：US09288094B2
公开(公告)日：2016-03-15
申请号：US14133123
申请日：2013-12-18
Applicant: Intel Corporation
Inventor： Bernard Arambepola , Parveen K. Shukla , Thushara Hewavithana
CPC classification number: H04L27/2646 , H04L5/0007 , H04L25/0218 , H04L25/022 , H04L25/0232 , H04L25/03343 , H04L27/2607 , H04L27/2613 , H04L27/2647 , H04L27/2665 , H04L27/2678
Abstract: One embodiment provides an apparatus. The apparatus includes an optimization module configured to determine a guard interval remainder based, at least in part on a comparison of an allowable microreflection interference level and an actual microreflection interference level; and a windowing module configured to window an OFDM (orthogonal frequency division multiplexed) symbol utilizing the guard interval remainder. The apparatus may further include a channel estimator module configured to determine a predicted channel frequency response based, at least in part, on a probing symbol; and a pre-equalizer module configured to pre-equalize the OFDM symbol based, at least in part, on the predicted channel frequency response.
Abstract translation: 一个实施例提供了一种装置。 该装置包括：优化模块，其被配置为至少部分地基于允许的微反射干扰电平与实际微反射干扰电平的比较来确定保护间隔余数; 以及窗口模块，被配置为利用所述保护间隔余数来对OFDM（正交频分复用）符号进行窗口化。 该装置还可以包括信道估计器模块，其被配置为至少部分地基于探测符号来确定预测的信道频率响应; 以及预均衡器模块，其被配置为至少部分地基于所预测的信道频率响应来预均衡所述OFDM符号。
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6.发明授权Systems and methods for implementing soft-decision Reed-Solomon decoding to improve cable modem and cable gateway performance 有权用于实现软判决Reed-Solomon解码以提高电缆调制解调器和电缆网关性能的系统和方法公开(公告)号：US08908810B2
公开(公告)日：2014-12-09
申请号：US13728022
申请日：2012-12-27
Applicant: Intel Corporation
Inventor： Bernard Arambepola , Murat Badem , Parveen K. Shukla , Sahan Gamage , Thushara Hewavithana , Naor Goldman
CPC classification number: H04L27/06 , H03M13/1515 , H03M13/451 , H03M13/453 , H04L1/0045 , H04L1/0047 , H04L1/0057 , H04L27/38
Abstract: A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. The algorithm is implemented in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. The soft Reed-Solomon (RS) decoding scheme extracts candidate RS symbols and their Log Likelihood Ratios (LLRs) from QAM symbols. The set of highest probable candidate blocks are then chosen and these are decoded using a variant of the Chase algorithm until a valid codeword is detected at the decoder output.
Abstract translation: 提供了一种用于实现软的里德 - 所罗门（RS）解码方案，技术或算法以改善电缆调制解调器和电缆网关中的物理层性能的系统和方法。 该算法在连接到QAM解调器的前向纠错（FEC）模块中实现。 实现RS解码方案，而不会使硬件或处理开销显着复杂化。 软里德 - 所罗门（RS）解码方案从QAM符号中提取候选RS符号及其对数似然比（LLR）。 然后选择最高可能候选块的集合，并且使用Chase算法的变体对这些候选块进行解码，直到在解码器输出处检测到有效码字。
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7.发明授权Apparatus, systems and methods utilizing adjacent-channel power dependent automatic gain control for digital television demodulation 有权利用用于数字电视解调的相邻信道功率依赖的自动增益控制的装置，系统和方法公开(公告)号：US08817195B2
公开(公告)日：2014-08-26
申请号：US14047098
申请日：2013-10-07
Applicant: Intel Corporation
Inventor： Parveen K. Shukla , Bernard Arambepola , Thushara Hewavithana , Sahan Gamage
IPC: H04N5/52
CPC classification number: H04N5/455 , H04N5/52 , H04N21/4382 , H04N21/6112
Abstract: An embodiment of the present invention provides a method for digital television demodulation, comprising using adjacent-channel power dependent automatic gain control (AGC) for the digital television demodulation, wherein an AGC technique takes into account a total power as well as power of adjacent channels to control gain of a gain control amplifier.
Abstract translation: 本发明的一个实施例提供一种用于数字电视解调的方法，包括对数字电视解调使用相邻信道功率依赖自动增益控制（AGC），其中AGC技术考虑到相邻信道的总功率和功率 以控制增益控制放大器的增益。
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8.发明申请ORTHOGONAL FREQUENCY DIVISION MULTIPLEX (OFDM) RECEIVER WITH PHASE NOISE MITIGATION AND REDUCED LATENCY 有权正弦波频分多址（OFDM）接收机，具有相位噪声缓解和减少延迟公开(公告)号：US20140211889A1
公开(公告)日：2014-07-31
申请号：US13997691
申请日：2011-12-20
Applicant: INTEL CORPORATION
Inventor： Bernard Arambepola , Thushara Hewavithana , Parveen K. Shukla , Sahan S. Gamage
CPC classification number: H04L27/2649 , H04L1/0036 , H04L27/265 , H04L27/2657 , H04L27/2675
Abstract: A system according to one embodiment includes a demodulator configured to receive an orthogonal frequency division multiplexed (OFDM) modulated signal comprising a current symbol and a sequence of previous symbols, each of the symbols comprising one or more pilot sub-carriers and one or more data sub-carriers; a phase angle computation circuit coupled to the demodulator, the phase angle computation circuit configured to compute a first mean, the first mean computed from the phase angle of one or more of the pilot sub-carriers of a predetermined number of the previous symbols; a predictive filter circuit coupled to the phase angle computation circuit, the predictive filter circuit configured to compute a second mean, the second mean estimating the phase angle of one or more sub-carriers of the current symbol, the estimation based on the first mean; and a phase noise cancelling circuit coupled to the predictive filter circuit, the phase noise cancelling circuit configured to correct the phase of one or more sub-carriers of the current symbol based on the second mean.
Abstract translation: 根据一个实施例的系统包括解调器，其被配置为接收包括当前符号和先前符号序列的正交频分复用（OFDM）调制信号，每个符号包括一个或多个导频子载波和一个或多个数据 子载体; 耦合到所述解调器的相位角计算电路，所述相位角计算电路被配置为计算第一平均值，所述第一平均值是从预定数量的先前符号的一个或多个导频子载波的相位角计算的第一平均值; 耦合到所述相位角计算电路的预测滤波器电路，所述预测滤波器电路被配置为计算第二平均值，所述第二平均值估计所述当前符号的一个或多个子载波的相位角，所述估计基于所述第一均值; 以及耦合到所述预测滤波器电路的相位噪声消除电路，所述相位噪声消除电路被配置为基于所述第二均值来校正所述当前符号的一个或多个子载波的相位。
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