公开(公告)号：US10446238B2

公开(公告)日：2019-10-15

申请号：US15717835

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  David B. Carlton ,  Purval S. Sule

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

公开(公告)号：US10325665B2

公开(公告)日：2019-06-18

申请号：US15836124

申请日：2017-12-08

Applicant: INTEL CORPORATION

Inventor： Richard Fastow ,  Xin Sun ,  Uday Chandrasekhar ,  Krishna K. Parat ,  Camila Jaramillo ,  Purval S. Sule ,  Aliasgar S. Madraswala

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/16 ,  G11C16/34 ,  G11C11/4074 ,  G11C16/04

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.