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公开(公告)号：US20170351534A1
公开(公告)日：2017-12-07
申请号：US15629882
申请日：2017-06-22
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC: G06F9/445 , G06F1/10 , G06F9/50 , G06F1/32 , G06F12/0891
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US09218046B2
公开(公告)日：2015-12-22
申请号：US14564436
申请日：2014-12-09
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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公开(公告)号：US08775834B2
公开(公告)日：2014-07-08
申请号：US13791089
申请日：2013-03-08
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US08738942B2
公开(公告)日：2014-05-27
申请号：US13721794
申请日：2012-12-20
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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Patent Agency Ranking
公开(公告)号：US20150095675A1
公开(公告)日：2015-04-02
申请号：US14564436
申请日：2014-12-09
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC: G06F1/32
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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公开(公告)号：US20160077844A1
公开(公告)日：2016-03-17
申请号：US14947321
申请日：2015-11-20
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US09715397B2
公开(公告)日：2017-07-25
申请号：US14947321
申请日：2015-11-20
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US09235256B2
公开(公告)日：2016-01-12
申请号：US14227680
申请日：2014-03-27
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US08924748B2
公开(公告)日：2014-12-30
申请号：US14141992
申请日：2013-12-27
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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