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公开(公告)号：US20180198709A1
公开(公告)日：2018-07-12
申请号：US15859301
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US09218046B2
公开(公告)日：2015-12-22
申请号：US14564436
申请日：2014-12-09
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。
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公开(公告)号：US08775834B2
公开(公告)日：2014-07-08
申请号：US13791089
申请日：2013-03-08
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US08738942B2
公开(公告)日：2014-05-27
申请号：US13721794
申请日：2012-12-20
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US09485178B2
公开(公告)日：2016-11-01
申请号：US14229545
申请日：2014-03-28
Applicant: Intel Corporation
Inventor： Srihari Makikeni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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Patent Agency Ranking
公开(公告)号：US20160077844A1
公开(公告)日：2016-03-17
申请号：US14947321
申请日：2015-11-20
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US10652147B2
公开(公告)日：2020-05-12
申请号：US15859301
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US20170351534A1
公开(公告)日：2017-12-07
申请号：US15629882
申请日：2017-06-22
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC: G06F9/445 , G06F1/10 , G06F9/50 , G06F1/32 , G06F12/0891
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US20170048142A1
公开(公告)日：2017-02-16
申请号：US15339354
申请日：2016-10-31
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
Abstract translation: 一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段 协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。 该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷 。 该方法还包括产生导致因特网协议分组的接收处理的信号。
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公开(公告)号：US09715397B2
公开(公告)日：2017-07-25
申请号：US14947321
申请日：2015-11-20
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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