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    Hardware for split data translation lookaside buffers
    2.
    发明授权
    Hardware for split data translation lookaside buffers 有权

    公开(公告)号：US11580031B2

    公开(公告)日：2023-02-14

    申请号：US16813346

    申请日：2020-03-09

    Applicant: INTEL CORPORATION

    Inventor： Stanislav Shwartsman ,  Igor Yanover ,  Assaf Zaltsman ,  Ron Rais

    IPC: G06F12/1027 ,  G06F9/30

    Abstract: Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.

    HARDWARE FOR SPLIT DATA TRANSLATION LOOKASIDE BUFFERS
    4.
    发明申请
    HARDWARE FOR SPLIT DATA TRANSLATION LOOKASIDE BUFFERS 有权

    公开(公告)号：US20210034544A1

    公开(公告)日：2021-02-04

    申请号：US16813346

    申请日：2020-03-09

    Applicant: INTEL CORPORATION

    Inventor： Stanislav Shwartsman ,  Igor Yanover ,  Assaf Zaltsman ,  Ron Rais

    IPC: G06F12/1027 ,  G06F9/30

    Abstract: Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.

    Prefetch filter cache for a processor
    7.
    发明授权
    Prefetch filter cache for a processor 有权

    公开(公告)号：US10579530B2

    公开(公告)日：2020-03-03

    申请号：US15168980

    申请日：2016-05-31

    Applicant: Intel Corporation

    Inventor： Stanislav Shwartsman ,  Ron Rais

    IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0875

    Abstract: In an embodiment, a processor includes a plurality of cores, with at least one core including prefetch logic. The prefetch logic comprises circuitry to: receive a prefetch request; compare the received prefetch request to a plurality of entries of a prefetch filter cache; and in response to a determination that the received prefetch request matches one of the plurality of entries of the prefetch filter cache, drop the received prefetch request. Other embodiments are described and claimed.

    Enhance memory access permission based on per-page current privilege level
    8.
    发明授权
    Enhance memory access permission based on per-page current privilege level 有权

    公开(公告)号：US10114768B2

    公开(公告)日：2018-10-30

    申请号：US15249521

    申请日：2016-08-29

    Applicant: Intel Corporation

    Inventor： Gur Hildesheim ,  Gilbert Neiger ,  Baiju V. Patel ,  Ron Rais

    IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1027

    Abstract: A processing system includes a processing core and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store a page table entry (PTE) comprising a mapping from a virtual memory page referenced by an application running on the processing core to an identifier of a memory frame of a memory, a first plurality of access permission flags associated with accessing the memory frame under a first privilege mode, and a second plurality of access permission flags associated with accessing the memory under a second privilege mode.

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