公开(公告)号：US20240427847A1

公开(公告)日：2024-12-26

申请号：US18757003

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

公开(公告)号：US20230281272A1

公开(公告)日：2023-09-07

申请号：US18301386

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30145 ,  G06F15/8046

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

公开(公告)号：US20220206795A1

公开(公告)日：2022-06-30

申请号：US17569229

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  VARGHESE GEORGE ,  JOYDEEP RAY ,  ASHUTOSH GARG ,  JORGE PARRA ,  SHUBH SHAH ,  SHUBRA MARWAHA

IPC: G06F9/30 ,  G06F9/50 ,  G06F17/16

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.

公开(公告)号：US20190265974A1

公开(公告)日：2019-08-29

申请号：US15903549

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： BUQI CHENG ,  WEI-YU CHEN ,  GUEI-YUAN LUEH ,  CHANDRA GURRAM ,  SUBRAMANIAM MAIYURAN

IPC: G06F9/30 ,  G06F9/48 ,  G06T1/20

Abstract: Mechanisms for reducing register bank conflicts based on software hint and hardware thread switch are disclosed. In some embodiments, an apparatus for thread switching includes a graphics processing unit (GPU) that includes a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts. A decoding circuitry checks a thread switching field of a first instruction to be executed by a first thread. The GPU performs a thread switch mechanism to cause a second instruction to be executed by a second thread when the thread switching field of the first instruction is set.

公开(公告)号：US20150309800A1

公开(公告)日：2015-10-29

申请号：US14261097

申请日：2014-04-24

Applicant: Intel Corporation

Inventor： WEI-YU CHEN ,  GUEI-YUAN LUEH ,  SUBRAMANIAM MAIYURAN ,  SUPRATIM PAL

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline has an instruction fetch stage to fetch an instruction specifying multiple target resultant registers. The instruction execution pipeline has an instruction decode stage to decode the instruction. The instruction execution pipeline has a functional unit to prepare resultant content specific to each of the multiple target resultant registers. The instruction execution pipeline has a write-back stage to write back said resultant content specific to each of said multiple target resultant registers.

Abstract translation: 描述了具有指令执行流水线的处理器。 指令执行流水线具有指令提取阶段，用于获取指定多个目标结果寄存器的指令。 指令执行流水线具有解码指令的指令解码级。 指令执行流水线具有功能单元，用于准备特定于多个目标结果寄存器中的每一个的结果内容。 所述指令执行流水线具有写回阶段，用于将所述结果内容写入到所述多个目标结果寄存器中的每个上。

公开(公告)号：US20230297373A1

公开(公告)日：2023-09-21

申请号：US18307088

申请日：2023-04-26

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  GUEI-YUAN LUEH ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  CHANDRA S. GURRAM ,  JORGE E. PARRA ,  JUNJIE GU ,  KONRAD TRIFUNOVIC ,  HONG BIN LIAO ,  MIKE B. MACPHERSON ,  SHUBH B. SHAH ,  SHUBRA MARWAHA ,  STEPHEN JUNKINS ,  TIMOTHY R. BAUER ,  VARGHESE GEORGE ,  WEIYU CHEN

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30145 ,  G06T1/20 ,  G06F9/3887 ,  G06F9/3802

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch a single instruction for execution, a decode unit to decode the single instruction into a decoded instruction, wherein the decoded instruction is to cause the graphics processing unit to perform a set of parallel dot product operations on elements of input matrices, and a systolic dot product unit to execute the decoded instruction across one or more parallel processor lanes using multiple systolic layers associated with multiple pipeline stages. The multiple pipeline stages include one or more sets of interconnected multipliers and adders to compute multiple concurrent dot products.

公开(公告)号：US20230029176A1

公开(公告)日：2023-01-26

申请号：US17868448

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALOPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210349966A1

公开(公告)日：2021-11-11

申请号：US16913800

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

公开(公告)号：US20210303299A1

公开(公告)日：2021-09-30

申请号：US17304153

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  GUEI-YUAN LUEH ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  CHANDRA S. GURRAM ,  JORGE E. PARRA ,  JUNJIE GU ,  KONRAD TRIFUNOVIC ,  HONG BIN LIAO ,  MIKE B. MACPHERSON ,  SHUBH B. SHAH ,  SHUBRA MARWAHA ,  STEPHEN JUNKINS ,  TIMOTHY R. BAUER ,  VARGHESE GEORGE ,  WEIYU CHEN

IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

公开(公告)号：US20210150770A1

公开(公告)日：2021-05-20

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06N3/04 ,  G06T15/00

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.