公开(公告)号：US20140229750A1

公开(公告)日：2014-08-14

申请号：US13976682

申请日：2012-03-13

Applicant: INTEL CORPORATION

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Samuel W. Ho ,  Scott P. Bobholz ,  Chris Poirier

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22 ,  Y02D10/24

Abstract: A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

Abstract translation: 一种处理器中每个核心性能状态的方法和装置。 每个核心性能状态（PCPS）是指在不同的电压和/频率点对各个内核的并行运行。 在本发明的一个实施例中，处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。 功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。 通过允许其内核具有每个核心性能状态配置，处理器能够降低其功耗并提高其性能。