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1.发明申请ADAPTIVE ALGORITHM FOR THERMAL THROTTLING OF MULTI-CORE PROCESSORS WITH NON-HOMOGENEOUS PERFORMANCE STATES 有权具有非均质性能状态的多核心处理器的热转移自适应算法公开(公告)号：US20160026231A1
公开(公告)日：2016-01-28
申请号：US14340802
申请日：2014-07-25
Applicant: Intel Corporation
Inventor： James S. Ignowski , Matthew M. Bace , Eric J. Dehaemer , Chris Poirier
CPC classification number: G06F1/206 , G06F1/26 , G06F1/28 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F11/0754 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括：多个核心，每个核心执行指令; 多个热传感器，其中至少一个与每个芯相关联; 以及耦合到所述芯的功率控制单元（PCU）。 PCU包括热控制逻辑，当第二核心的温度超过至少一个热阈值时，预先将第一核心节流第一节流量。 注意，该第一核心可以独立于第二核心的节流被预先节流，并且可以具有第一核心的温度不超过任何热阈值。 描述和要求保护其他实施例。
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2.发明申请公开(公告)号：US20170123467A1
公开(公告)日：2017-05-04
申请号：US15401276
申请日：2017-01-09
Applicant: Intel Corporation
Inventor： James S. Ignowski , Matthew M. Bace , Eric J. Dehaemer , Chris Poirier
CPC classification number: G06F1/206 , G06F1/26 , G06F1/28 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F11/0754 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.
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公开(公告)号：US09405351B2
公开(公告)日：2016-08-02
申请号：US13716712
申请日：2012-12-17
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
CPC classification number: G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F9/5044 , G06F9/505 , G06F13/00 , G06F15/17325 , G06T1/20 , Y02D10/126
Abstract: In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。 功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。 描述和要求保护其他实施例。
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公开(公告)号：US20140229750A1
公开(公告)日：2014-08-14
申请号：US13976682
申请日：2012-03-13
Applicant: INTEL CORPORATION
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Samuel W. Ho , Scott P. Bobholz , Chris Poirier
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
Abstract: A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.
Abstract translation: 一种处理器中每个核心性能状态的方法和装置。 每个核心性能状态（PCPS）是指在不同的电压和/频率点对各个内核的并行运行。 在本发明的一个实施例中，处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。 功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。 通过允许其内核具有每个核心性能状态配置，处理器能够降低其功耗并提高其性能。
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5.发明授权公开(公告)号：US10345884B2
公开(公告)日：2019-07-09
申请号：US15238717
申请日：2016-08-16
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don C. Soltis, Jr. , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC: G06F9/00 , G06F1/3234 , G06F1/20 , G06F1/3206 , G06F1/28
Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
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Patent Agency Ranking
公开(公告)号：US10331186B2
公开(公告)日：2019-06-25
申请号：US15401276
申请日：2017-01-09
Applicant: Intel Corporation
Inventor： James S. Ignowski , Matthew M. Bace , Eric J. Dehaemer , Chris Poirier
IPC: G06F1/20 , G06F1/26 , G06F1/28 , G06F9/50 , G06F1/324 , G06F11/07 , G06F1/3206 , G06F1/3234 , G06F1/3293 , G06F1/3296
Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.
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7.发明授权公开(公告)号：US09377841B2
公开(公告)日：2016-06-28
申请号：US13889785
申请日：2013-05-08
Applicant: Intel Corporation
Inventor： Ankush Varma , Ian Steiner , Avinash Ananthakrishnan , Krishnakanth Sistla , Chris Poirier , Matthew Bace , Eric Dehaemer
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3206 , Y02D10/126
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元以控制处理器的功率消耗，其中功率控制单元包括控制逻辑以减少最大操作 如果在第一时间段内发生第一数量的强制执行状态转换或在第二时间段内发生第二数量的强制执行状态转换，则处理器的频率。 描述和要求保护其他实施例。
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8.发明授权Mechanism to provide workload and configuration-aware deterministic performance for microprocessors 有权为微处理器提供工作负载和配置感知确定性性能的机制公开(公告)号：US09417681B2
公开(公告)日：2016-08-16
申请号：US14697541
申请日：2015-04-27
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Martin T. Rowland , Chris Poirier , Eric J. Dehaemer , Avinash N. Ananthakrishnan , Jeremy J. Shrall , Xiuting C. Man , Stephen H. Gunther , Krishna K. Rangan , Devadatta V. Bodas , Don Soltis , Hang T. Nguyen , Cyprian W. Woo , Thi Dang
IPC: G06F15/177 , G06F1/32 , G06F1/00 , G06F1/20
CPC classification number: G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
Abstract translation: 装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。 片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。
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公开(公告)号：US09268393B2
公开(公告)日：2016-02-23
申请号：US13997295
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
CPC classification number: G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。
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10.发明授权Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states 有权具有非均匀性能状态的多核处理器的热节流自适应算法公开(公告)号：US09575537B2
公开(公告)日：2017-02-21
申请号：US14340802
申请日：2014-07-25
Applicant: Intel Corporation
Inventor： James S. Ignowski , Matthew M. Bace , Eric J. Dehaemer , Chris Poirier
CPC classification number: G06F1/206 , G06F1/26 , G06F1/28 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F11/0754 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括：多个核心，每个核心执行指令; 多个热传感器，其中至少一个与每个芯相关联; 以及耦合到所述芯的功率控制单元（PCU）。 PCU包括热控制逻辑，当第二核心的温度超过至少一个热阈值时，预先将第一核心节流第一节流量。 注意，该第一核心可以独立于第二核心的节流被预先节流，并且可以具有第一核心的温度不超过任何热阈值。 描述和要求保护其他实施例。
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