公开(公告)号：US20200350817A1

公开(公告)日：2020-11-05

申请号：US16642853

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vivek DE ,  Krishnan RAVICHANDRAN ,  Harish KRISHNAMURTHY ,  Khondker AHMED ,  Sriram VANGAL ,  Vaibhav VAIDYA ,  Turbo MAJUMDER ,  Christopher SCHAEF ,  Suhwan KIM ,  Xiaosen LIU ,  Nachiket DESAI

IPC: H02M3/07

Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

公开(公告)号：US20200183922A1

公开(公告)日：2020-06-11

申请号：US16795516

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Wootaek LIM ,  Minchang CHO ,  Somnath PAUL ,  Charles AUGUSTINE ,  Suyoung BANG ,  Turbo MAJUMDER ,  Muhammad M. KHELLAH

IPC: G06F16/2453 ,  G06F7/08 ,  G06F7/20 ,  G11C15/04

Abstract: An apparatus is described. The apparatus includes a nearest neighbor search circuit to perform a search according to a first stage search and a second stage search. The nearest neighbor search circuit includes a first stage circuit and a second stage circuit. The first stage search circuit includes a hash logic circuit and a content addressable memory. The hash logic circuit is to generate a hash word from a input query vector. The hash word has B bands. The content addressable memory is to store hashes of a random access memory's data items. The hashes each have B bands. The content addressable memory is to compare the hashes against the hash word on a sequential band-by-band basis. The second stage circuit char the random access memory and a compare and sort circuit. The compare and sort circuit is to receive the input query vector. The random access memory has crosswise bit lines coupled to the compare and sort circuit. The compare and sort circuit is to identify k nearest ones of the data items whose hashes were selected by the content addressable memory.

公开(公告)号：US20190043583A1

公开(公告)日：2019-02-07

申请号：US16110990

申请日：2018-08-23

Applicant: INTEL CORPORATION

Inventor： Turbo MAJUMDER ,  Somnath PAUL ,  Charles AUGUSTINE ,  Muhammad M. KHELLAH

IPC: G11C15/04 ,  G11C8/10 ,  G06F17/30 ,  G06T1/60

Abstract: Provided are an apparatus, video processing unit, and method for clustering events in a content addressable memory. An event is received including at least one parameter value and a timestamp. A determination is made as to whether there is a valid entry in the memory having at least one parameter value within a predefined range of values of the at least one parameter value in the event. In response to a determination that there is the valid entry, writing the at least one parameter value and the timestamp in the event to the valid entry.