公开(公告)号：US20200218676A1

公开(公告)日：2020-07-09

申请号：US16825538

申请日：2020-03-20

Applicant: Intel Corporation

Inventor： Gang CAO ,  James R. HARRIS ,  Ziye YANG ,  Vishal VERMA ,  Changpeng LIU ,  Chong HAN ,  Benjamin WALKER

IPC: G06F13/16 ,  G06F9/50

Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.

公开(公告)号：US20180089099A1

公开(公告)日：2018-03-29

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok RAJ ,  Sivakumar RADHAKRISHNAN ,  Dan J. WILLIAMS ,  Vishal VERMA ,  Narayan RANGANATHAN ,  Chet R. DOUGLAS

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/65

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.