公开(公告)号：US10831658B2

公开(公告)日：2020-11-10

申请号：US16239455

申请日：2019-01-03

Applicant: INTEL CORPORATION

Inventor： Yanru Li ,  Chia-Hung Kuo ,  Ali Taha

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0853 ,  G06F12/126 ,  G06F12/0811 ,  G06F12/0868

Abstract: Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

公开(公告)号：US11144467B2

公开(公告)日：2021-10-12

申请号：US16416036

申请日：2019-05-17

Applicant: Intel Corporation

Inventor： Yanru Li ,  Ali Taha ,  Chia-Hung S. Kuo

IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0891

Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

公开(公告)号：US11886910B2

公开(公告)日：2024-01-30

申请号：US16728175

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Yanru Li ,  William Zand ,  Thomas Klingenbrunn ,  Ali Taha

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/1009 ,  G06F13/16

CPC classification number: G06F9/4881 ,  G06F9/466 ,  G06F12/1009 ,  G06F13/1605 ,  G06F2213/0038

Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

公开(公告)号：US20210200579A1

公开(公告)日：2021-07-01

申请号：US16728175

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Yanru Li ,  William Zand ,  Thomas Klingenbrunn ,  Ali Taha

IPC: G06F9/48 ,  G06F9/46 ,  G06F13/16 ,  G06F12/1009

Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

公开(公告)号：US20190272236A1

公开(公告)日：2019-09-05

申请号：US16416036

申请日：2019-05-17

Applicant: Intel Corporation

Inventor： Yanru Li ,  Ali Taha ,  Chia-Hung S. Kuo

IPC: G06F12/0888 ,  G06F12/0891

Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.