中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.014 seconds)

    REDUCING MEMORY POWER USAGE IN FAR MEMORY
    5.
    发明申请
    REDUCING MEMORY POWER USAGE IN FAR MEMORY 有权

    公开(公告)号：US20230086149A1

    公开(公告)日：2023-03-23

    申请号：US17483491

    申请日：2021-09-23

    Applicant: Intel Corporation

    Inventor： Chia-Hung S. Kuo ,  Deepak Gandiga Shivakumar ,  Anoop Mukker ,  Arik Gihon ,  Zvika Greenfield ,  Asaf Rubinstein ,  Leo Aqrabawi

    IPC: G06F12/0804 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3287

    Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.

    MANAGEMENT OF MULTIPLE INTERFACE PORTS
    6.
    发明申请
    MANAGEMENT OF MULTIPLE INTERFACE PORTS 审中-公开

    公开(公告)号：US20180225272A1

    公开(公告)日：2018-08-09

    申请号：US15632212

    申请日：2017-06-23

    Applicant: Intel Corporation

    Inventor： Vijaykumar B. Kadgi ,  Venkataramani Gopalakrishnan ,  Basavaraj B. Astekar ,  Chia-Hung S. Kuo ,  Nivedita Aggarwal

    IPC: G06F17/24 ,  G06F17/30 ,  G06F9/44

    CPC classification number: G06F17/243 ,  G06F9/4403 ,  G06F9/451 ,  G06F16/95

    Abstract: Embodiments may include systems and methods for managing multiple ports of a computing interface. A computing device may include a connector with a power port and a data port. A connector manager may identify whether a port partner is coupled to the connector, identify an inquiry related to a status of the connector, where the inquiry may be received from a BIOS of the computing device. In addition, the connector manager may generate an indication of the status of the connector, and further transmit the indication of the status of the connector to the BIOS. A BIOS may identify that a data device coupled to the connector through a port partner is to be initialized, and further transmit to a connector manager an inquiry related to a status of the connector, before initializing the data device. Other embodiments may be described and/or claimed.

    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO GENERATE DYNAMIC COMPUTING RESOURCE SCHEDULES
    7.
    发明申请
    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO GENERATE DYNAMIC COMPUTING RESOURCE SCHEDULES 有权

    公开(公告)号：US20250021381A1

    公开(公告)日：2025-01-16

    申请号：US18902104

    申请日：2024-09-30

    Applicant: Intel Corporation

    Inventor： Sangeeta Manepalli ,  Chia-Hung S. Kuo ,  Venkateshan Udhayan ,  Stanley Baran ,  Jason Tanner ,  Michael Rosenzweig

    IPC: G06F9/48

    Abstract: Methods, systems, articles of manufacture and apparatus are disclosed to generate dynamic computing resource schedules. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to determine a first schedule policy based on (a) an interval parameter and (b) an energy budget parameter, the first schedule policy to include a first instantiation window. The example instructions further determine performance metrics of a target processor circuit based on instantiating a workload with the first schedule policy, and generate a second schedule policy based on the performance metrics of the target processor circuit, the second schedule policy to include a second instantiation window, the second instantiation window including a modification relative to the first instantiation window.

    Bypassing cache memory in a write transaction in a system with multi-level memory
    10.
    发明授权
    Bypassing cache memory in a write transaction in a system with multi-level memory 有权

    公开(公告)号：US11144467B2

    公开(公告)日：2021-10-12

    申请号：US16416036

    申请日：2019-05-17

    Applicant: Intel Corporation

    Inventor： Yanru Li ,  Ali Taha ,  Chia-Hung S. Kuo

    IPC: G06F12/00 ,  G06F12/0888 ,  G06F12/0891

    Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

Patent Agency Ranking