公开(公告)号：US20230325241A1

公开(公告)日：2023-10-12

申请号：US18043259

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Andrew J. HERDRICH ,  Yen-Cheng LIU ,  Venkateswara MADDURI ,  Krishnakumar K. GANAPATHY ,  Edwin VERPLANKE ,  Christopher GIANOS ,  Hanna ALAM ,  Joseph NUZMAN ,  Larisa NOVAKOVSKY

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F2209/504

Abstract: Embodiments for allocating shared resources are disclosed. In an embodiment, an apparatus includes a core and a hardware rate selector. The hardware rate selector is to, in response to a first indication that demand for memory bandwidth from the core has reached a threshold value, determine a delay value to be used to limit allocation of memory bandwidth to the core. The hardware rate selector includes a controller having a first counter to count a second indication of demand for memory bandwidth from the first core and a second counter to count expirations of time windows. The first indication is based on a difference between the first counter value and the second counter value.

公开(公告)号：US20210224190A1

公开(公告)日：2021-07-22

申请号：US17223994

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Vinit MATHEW ABRAHAM ,  Yen-Cheng LIU

IPC: G06F12/0815

Abstract: Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and receiving a second memory rule programming. In some examples, a mask is applied to reject the first memory rule programming; and applying the mask to accept the second memory rule programming and program the memory rule for the home agent.

公开(公告)号：US20210064117A1

公开(公告)日：2021-03-04

申请号：US17097325

申请日：2020-11-13

Applicant: INTEL CORPORATION

Inventor： Yen-Cheng LIU ,  P. Keong OR ,  Krishnakanth V. SISTLA ,  Ganapati SRINIVASA

IPC: G06F1/3234 ,  G06F1/20 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/324 ,  G06F15/80 ,  G06F1/3206 ,  G06F12/0811 ,  G11C7/10

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

公开(公告)号：US20200301830A1

公开(公告)日：2020-09-24

申请号：US16894402

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Vinit MATHEW ABRAHAM ,  Jeffrey D. CHAMBERLAIN ,  Yen-Cheng LIU ,  Eswaramoorthi NALLUSAMY ,  Soumya S. EACHEMPATI

IPC: G06F12/0802 ,  G06F13/40 ,  G06F13/16

Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.