公开(公告)号：US20190384348A1

公开(公告)日：2019-12-19

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan SRINIVASAN ,  Krishnakanth V. SISTLA ,  Corey D. GOUGH ,  Ian M. STEINER ,  Nikhil GUPTA ,  Vivek GARG ,  Ankush VARMA ,  Sujal A. VORA ,  David P. LERNER ,  Joseph M. SULLIVAN ,  Nagasubramanian GURUMOORTHY ,  William J. BOWHILL ,  Venkatesh RAMAMURTHY ,  Chris MACNAMARA ,  John J. BROWNE ,  Ripan DAS

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20190042348A1

公开(公告)日：2019-02-07

申请号：US15859474

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Anand K. ENAMANDRAM ,  Eswaramoorthi NALLUSAMY ,  Russell J. WUNDERLICH ,  Krishnakanth V. SISTLA

IPC: G06F11/07

Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

公开(公告)号：US20210064117A1

公开(公告)日：2021-03-04

申请号：US17097325

申请日：2020-11-13

Applicant: INTEL CORPORATION

Inventor： Yen-Cheng LIU ,  P. Keong OR ,  Krishnakanth V. SISTLA ,  Ganapati SRINIVASA

IPC: G06F1/3234 ,  G06F1/20 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/324 ,  G06F15/80 ,  G06F1/3206 ,  G06F12/0811 ,  G11C7/10

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

公开(公告)号：US20160018883A1

公开(公告)日：2016-01-21

申请号：US14867490

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Ankush VARMA ,  Krishnakanth V. SISTLA ,  Cesar A. QUIROZ ,  Vivek GARG ,  Martin T. ROWLAND ,  Inder M. SODHI ,  James S. BURNS

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.