公开(公告)号：US20190250697A1

公开(公告)日：2019-08-15

申请号：US16396557

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Adrian MOCANU ,  Andrew MORNING-SMITH ,  Zeljko ZUPANC ,  Derrick WILSON

IPC: G06F1/3296 ,  G06F3/06 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.

公开(公告)号：US20170177374A1

公开(公告)日：2017-06-22

申请号：US14975272

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Andrew MORNING-SMITH ,  Adrian MOCANU ,  Zeljko ZUPANC ,  Mike M. NGO

IPC: G06F9/44 ,  G06F1/30 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F11/1441 ,  G06F1/263 ,  G06F1/305 ,  G06F9/442 ,  G06F13/4022

Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to an input power module of the non-volatile memory, and a power management module configurable to determine whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line. Provided also is a computational device that includes the memory device. Provided also is a method in which a power management module of the memory device determines whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line.

公开(公告)号：US20190041938A1

公开(公告)日：2019-02-07

申请号：US16047358

申请日：2018-07-27

Applicant: Intel Corporation

Inventor： Zeljko ZUPANC ,  Andrew MORNING-SMITH ,  Mary GOODMAN ,  Alice ALLEN ,  Simon RAMAGE ,  Justin ELKOW

IPC: G06F1/30 ,  H02J7/00 ,  G01R31/40 ,  G01R31/36

Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.