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    EFFICIENT GENERATION OF INSTRUMENTATION DATA FOR DIRECT MEMORY ACCESS OPERATIONS
    1.
    发明申请
    EFFICIENT GENERATION OF INSTRUMENTATION DATA FOR DIRECT MEMORY ACCESS OPERATIONS 有权

    公开(公告)号：US20210216430A1

    公开(公告)日：2021-07-15

    申请号：US16738311

    申请日：2020-01-09

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Matthias Klein ,  Deanna P. D. Berger ,  Craig R. Walters

    IPC分类号： G06F11/34 ,  G06F13/28 ,  G06F11/30

    摘要： Aspects of the invention include efficient generation of instrumentation data for direct memory access operations. A non-limiting example apparatus includes an instrumentation component, residing in a cache in communication with a plurality of processing units, an accelerator, and a plurality of input output interfaces. The cache includes a direct memory access monitor that receives events from the accelerator its respective I/O interface and stores DMA state and latency for each event. The cache also includes a bucket including a DMA counter and a latency counter in communication with the DMA monitor, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.

    MEMORY STATE INDICATOR CHECK OPERATIONS
    4.
    发明申请
    MEMORY STATE INDICATOR CHECK OPERATIONS 审中-公开
    记忆状态指示灯检查操作

    公开(公告)号：US20170003886A1

    公开(公告)日：2017-01-05

    申请号：US14755732

    申请日：2015-06-30

    申请人： International Business Machines Corporation

    发明人： Pak-kin Mak ,  Timothy J. Slegel ,  Craig R. Walters ,  Charles F. Webb

    IPC分类号： G06F3/06 ,  G06F12/08

    CPC分类号： G06F3/067 ,  G06F3/0605 ,  G06F9/5016 ,  Y02D10/22

    摘要： Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state.

    摘要翻译： 方面包括计算机实现的方法，包括在处理器处接收指令以对具有地址的存储器块执行操作，并且由处理器访问状态指示符，而不改变状态指示符的值。 状态指示符存储在独立于存储器块的存储位置中，并且访问包括向操作者发送请求以将状态指示符的值返回到处理器。 该方法还包括基于状态指示符的值来确定存储器块是否处于预定义状态。

    DUAL/MULTI-MODE PROCESSOR PIPELINE SAMPLING
    5.
    发明申请
    DUAL/MULTI-MODE PROCESSOR PIPELINE SAMPLING 审中-公开
    双/多模式处理器管道采样

    公开(公告)号：US20150261569A1

    公开(公告)日：2015-09-17

    申请号：US14208257

    申请日：2014-03-13

    申请人： International Business Machines Corporation

    发明人： Deanna Postles Dunn Berger ,  Kathryn M. Jackson ,  Joshua D. Massover ,  Gary E. Strait ,  Hanno Ulrich ,  Craig R. Walters

    IPC分类号： G06F9/48

    CPC分类号： G06F9/4881 ,  G06F11/30 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3409 ,  G06F11/3476 ,  G06F11/348

    摘要： Embodiments are directed to systems and methodologies for efficiently sampling data for analysis by a pipeline analysis algorithm. The amount of sampled data is maximized without increasing sampling overhead by sampling “non-pipeline activity” data if the subject pipeline is inactive during the sampling time. The non-pipeline activity data is selected to include overall system information that is relevant to the subject pipeline's performance but is not necessarily dependent on whether the subject pipeline is active. In some embodiments, the non-pipeline activity data allows for confirmation of a pipeline performance characteristic that must otherwise be inferred by the subsequent pipeline analysis algorithm from data sampled while the pipeline was active. In some embodiments, the non-pipeline activity data allows the pipeline analysis algorithm to analyze additional performance characteristics that cannot otherwise be inferred from the data sampled while the pipeline was active.

    摘要翻译： 实施例涉及用于通过流水线分析算法有效地采样数据进行分析的系统和方法。 如果在采样时间内主体管线不活动，则采样数据的数量最大化，而不会通过采样“非流水线活动”数据而增加采样开销。 选择非流水线活动数据以包括与主体管线的性能相关的整体系统信息，但不一定取决于主体流水线是否活动。 在一些实施例中，非流水线活动数据允许确认流水线性能特征，否则在流水线活动时，必须由随后的流水线分析算法从采样的数据中推断。 在一些实施例中，非流水线活动数据允许流水线分析算法分析在流水线处于活动状态时所采样的数据不能被推断的附加性能特征。

    USING A PREDETERMINED BIT TO REPRESENT A PREDETERMINED PATTERN IN A CACHE LINE
    6.
    发明公开
    USING A PREDETERMINED BIT TO REPRESENT A PREDETERMINED PATTERN IN A CACHE LINE 审中-公开

    公开(公告)号：US20240202117A1

    公开(公告)日：2024-06-20

    申请号：US18083271

    申请日：2022-12-16

    申请人： International Business Machines Corporation

    发明人： Bulent Abali ,  Alper Buyuktosunoglu ,  Ashutosh Mishra ,  David Trilla Rodriguez ,  Craig R. Walters

    IPC分类号： G06F12/0802

    CPC分类号： G06F12/0802 ,  G06F2212/1024

    摘要： A computer-implemented method, according to one embodiment, includes determining that a first predetermined pattern is to be written to a first cache line of a cache. In response to the determination, a first bit is set in a first directory instead of writing the first predetermined pattern in the first cache line. The first bit is associated with the first cache line in the first directory. A computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method. A system, according to another embodiment, includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to perform the foregoing method.

    Controller address contention assumption
    7.
    发明授权
    Controller address contention assumption 有权

    公开(公告)号：US11461151B2

    公开(公告)日：2022-10-04

    申请号：US17237167

    申请日：2021-04-22

    申请人： International Business Machines Corporation

    发明人： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

    IPC分类号： G06F9/52 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/54 ,  G06F9/38

    摘要： Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

    CONTROLLER ADDRESS CONTENTION ASSUMPTION
    8.
    发明申请
    CONTROLLER ADDRESS CONTENTION ASSUMPTION 有权

    公开(公告)号：US20210240548A1

    公开(公告)日：2021-08-05

    申请号：US17237167

    申请日：2021-04-22

    申请人： International Business Machines Corporation

    发明人： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

    IPC分类号： G06F9/52 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/54 ,  G06F9/38

    摘要： Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.