利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

64 条记录 (耗时 0.022 秒)

    LOAD INSTRUCTION WITH TIMEOUT
    2.
    发明申请
    LOAD INSTRUCTION WITH TIMEOUT 审中-公开

    公开(公告)号：US20200379760A1

    公开(公告)日：2020-12-03

    申请号：US16423713

    申请日：2019-05-28

    申请人： International Business Machines Corporation

    发明人： Christian Jacobi ,  Matthias Klein ,  Martin Recktenwald ,  Anthony Saporito ,  Robert J. Sonnelitter, III

    IPC分类号： G06F9/30 ,  G06F12/0815

    摘要： In one example implementation according to aspects of the present disclosure, a computer-implemented method for executing a load instruction with a timeout includes receiving, by a processing device, the load instruction. The method further includes attempting, by the processing device, to load a lock on a cache line of a memory. The method further includes determining, by the processing device, whether the timeout has expired prior to a successful loading of the lock on the cache line. The method further includes , responsive to determining that the timeout has expired, executing, by the processing device, another instruction instead of loading the lock on the cache line.

    PREINSTALL OF PARTIAL STORE CACHE LINES
    4.
    发明申请
    PREINSTALL OF PARTIAL STORE CACHE LINES 审中-公开

    公开(公告)号：US20180374522A1

    公开(公告)日：2018-12-27

    申请号：US15629923

    申请日：2017-06-22

    申请人： International Business Machines Corporation

    发明人： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

    IPC分类号： G11C8/06 ,  G06F3/06 ,  G06F13/16

    摘要： A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

    EDRAM refresh in a high performance cache architecture
    8.
    发明授权
    EDRAM refresh in a high performance cache architecture 有权
    EDRAM在高性能缓存架构中刷新

    公开(公告)号：US09189415B2

    公开(公告)日：2015-11-17

    申请号：US13657100

    申请日：2012-10-22

    申请人： International Business Machines Corporation

    发明人： Michael Fee ,  Arthur J. O'Neill, Jr. ,  Robert J. Sonnelitter, III

    IPC分类号： G06F13/14 ,  G06F12/02 ,  G06F12/08 ,  G06F13/16 ,  G11C11/406

    CPC分类号： G06F12/0893 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C2207/104

    摘要： A method for implementing embedded dynamic random access memory (eDRAM) refreshing in a high performance cache architecture. The method includes receiving a memory access request, via a cache controller, from a memory refresh requestor, the memory access request for a memory address range in a cache memory. The method also includes detecting that the cache memory located at the memory address range is available to receive the memory access request and sending the memory access request to a memory request interpreter. The method further includes receiving the memory access request from the cache controller, determining that the memory access request is a request to refresh contents of the memory address range in the cache memory, and refreshing data in the memory address range.

    摘要翻译： 一种用于在高性能高速缓存架构中实现嵌入式动态随机存取存储器（eDRAM）刷新的方法。 该方法包括经由高速缓存控制器从存储器刷新请求器接收对高速缓冲存储器中的存储器地址范围的存储器访问请求的存储器访问请求。 该方法还包括检测位于存储器地址范围的高速缓冲存储器可用于接收存储器访问请求并将存储器访问请求发送到存储器请求解释器。 该方法还包括从高速缓存控制器接收存储器访问请求，确定存储器访问请求是刷新高速缓冲存储器中的存储器地址范围的内容的请求，以及刷新存储器地址范围中的数据。

    EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE
    9.
    发明申请
    EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE 有权
    EDRAM在高性能缓存架构中刷新

    公开(公告)号：US20130046926A1

    公开(公告)日：2013-02-21

    申请号：US13657100

    申请日：2012-10-22

    申请人： International Business Machines Corporation

    发明人： Michael Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0893 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C2207/104

    摘要： A method for implementing embedded dynamic random access memory (eDRAM) refreshing in a high performance cache architecture. The method includes receiving a memory access request, via a cache controller, from a memory refresh requestor, the memory access request for a memory address range in a cache memory. The method also includes detecting that the cache memory located at the memory address range is available to receive the memory access request and sending the memory access request to a memory request interpreter. The method further includes receiving the memory access request from the cache controller, determining that the memory access request is a request to refresh contents of the memory address range in the cache memory, and refreshing data in the memory address range.

    摘要翻译： 一种用于在高性能高速缓存架构中实现嵌入式动态随机存取存储器（eDRAM）刷新的方法。 该方法包括经由高速缓存控制器从存储器刷新请求器接收对高速缓冲存储器中的存储器地址范围的存储器访问请求的存储器访问请求。 该方法还包括检测位于存储器地址范围的高速缓冲存储器可用于接收存储器访问请求并将存储器访问请求发送到存储器请求解释器。 该方法还包括从高速缓存控制器接收存储器访问请求，确定存储器访问请求是刷新高速缓冲存储器中的存储器地址范围的内容的请求，以及刷新存储器地址范围中的数据。