公开(公告)号：US20240355382A1

公开(公告)日：2024-10-24

申请号：US18302117

申请日：2023-04-18

Applicant: International Business Machines Corporation

Inventor： Noam Jungmann ,  Elazar Kachir ,  Bishan He ,  Rajiv Joshi ,  Dureseti Chidambarrao ,  Baozhen Li ,  Atsushi Ogino ,  Klimentiy Shimanovich

IPC: G11C11/417

CPC classification number: G11C11/417

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

公开(公告)号：US11437312B2

公开(公告)日：2022-09-06

申请号：US16785454

申请日：2020-02-07

Applicant: International Business Machines Corporation

Inventor： Jim Shih-Chun Liang ,  Naftali E Lustig ,  Atsushi Ogino ,  Nan Jing

IPC: H01L23/522 ,  H01L21/3105 ,  H01L49/02 ,  H01L23/528

Abstract: A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.

公开(公告)号：US20210249349A1

公开(公告)日：2021-08-12

申请号：US16785454

申请日：2020-02-07

Applicant: International Business Machines Corporation

Inventor： Jim Shih-Chun Liang ,  Naftali E Lustig ,  Atsushi Ogino ,  Nan Jing

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/3105

Abstract: A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.

公开(公告)号：US20170005037A1

公开(公告)日：2017-01-05

申请号：US14755440

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jim S. Liang ,  Justin C. Long ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/7688 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

Abstract translation: 形成半导体结构的方法包括形成包含嵌入其中的第一金属层和半导体衬底的表面上的第一绝缘层。 该方法还包括在第一绝缘层上形成层间介电层（ILD）层，以及在ILD层中形成包括第一金属化沟槽和通孔的至少一个通孔沟槽结构。 此外，该方法还包括沉积金属材料以在第一金属化沟槽中形成第一金属化层，在通孔中形成通孔接触，并且在开口中的第一金属层的至少一部分的顶部上形成第二金属层 的第一绝缘层。 第一金属层和第二金属层构成位于第一绝缘层的开口中的多层金属接触。

公开(公告)号：US11308257B1

公开(公告)日：2022-04-19

申请号：US17122550

申请日：2020-12-15

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  David Wolpert ,  Atsushi Ogino ,  Matthew T. Guzowski ,  Steven Paul Ostrander ,  Tuhin Sinha ,  Michael Stewart Gray

IPC: G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  H01L23/48 ,  G06F119/14

Abstract: A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

公开(公告)号：US20250072017A1

公开(公告)日：2025-02-27

申请号：US18455665

申请日：2023-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Atsushi Ogino ,  Baozhen Li ,  Dureseti Chidambarrao ,  Matthew Stephen Angyal

IPC: H01G4/06 ,  H01L23/522

Abstract: A MIM capacitor including a bottom metal layer on a substrate, a first contact window in the bottom metal layer; and a first dielectric spacer disposed within the first contact window on vertical sidewalls of the bottom metal layer, where the first dielectric spacer has a rounded upper surface, where a bottom most surface of the bottom metal layer is substantially flush with a bottom most surface of the first insulator layer. A method including forming a bottom metal layer on a substrate, forming a first contact window in the bottom metal layer, and forming a first dielectric spacer disposed within the first contact window on vertical sidewalls of the bottom metal layer, wherein the first dielectric spacer has a rounded upper surface.

公开(公告)号：US09991202B2

公开(公告)日：2018-06-05

申请号：US14755440

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jim S. Liang ,  Justin C. Long ,  Atsushi Ogino

IPC: H01L21/76 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/7688 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.