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公开(公告)号：US20170212786A1
公开(公告)日：2017-07-27
申请号：US15284647
申请日：2016-10-04
发明人： EMRAH ACAR , JANE H. BARTIK , ALPER BUYUKTOSUNOGLU , BRIAN R. PRASKY , VIJAYALAKSHMI SRINIVASAN , JOHN-DAVID WELLMAN
CPC分类号： G06F11/3447 , G06F9/466 , G06F9/4887 , G06F11/3017 , G06F2201/88
摘要： The disclosed herein relates to a method of dynamic simultaneous multithreading metering for a plurality of independent threads being multithreaded. The method is executable by a processor. The method includes collecting attributes from processor and building a model utilizing the attributes. The method also includes performing the dynamic simultaneous multithreading metering in accordance with the model to output metering estimates for a first thread of the plurality of independent threads being multithreaded and updating the model based on the metering estimates.
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公开(公告)号：US20170206085A1
公开(公告)日：2017-07-20
申请号：US15433032
申请日：2017-02-15
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F5/00 , G06F7/584 , G06F9/30032 , G06F9/30098 , G06F9/30101 , G06F9/30134
摘要： A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.
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公开(公告)号：US20180143830A1
公开(公告)日：2018-05-24
申请号：US15873931
申请日：2018-01-18
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F5/00 , G06F7/584 , G06F9/30032 , G06F9/30098 , G06F9/30101 , G06F9/30134
摘要： A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.
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公开(公告)号：US20170344371A1
公开(公告)日：2017-11-30
申请号：US15165395
申请日：2016-05-26
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/30021 , G06F9/30054 , G06F9/30134 , G06F9/30145 , G06F9/324 , G06F9/34 , G06F9/3806
摘要： Examples of techniques for distance-based branch prediction are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes: determining, by a processing system, a potential return instruction address (IA) by determining whether a relationship is satisfied between a first target IA and a first branch IA; storing a second branch IA as a return when a target IA of a second branch matches a potential return IA for the second branch; and applying the potential return IA for the second branch as a predicted target IA of a predicted branch IA stored as a return.
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公开(公告)号：US20180203704A1
公开(公告)日：2018-07-19
申请号：US15405402
申请日：2017-01-13
发明人： JAMES J. BONANNO , BRIAN R. PRASKY
IPC分类号： G06F9/38 , G06F12/0875 , G06F12/0864
CPC分类号： G06F9/3844 , G06F9/3848 , G06F12/0875 , G06F2212/452
摘要： Embodiments include a technique for caching of perceptron branch patterns using ternary content addressable memory. The technique includes defining a table of perceptrons, each perceptron having a plurality of weights with each weight being associated with a bit location in a history vector, and defining a TCAM, the TCAM having a number of entries, wherein each entry includes a number of bit pairs, the number of bit pairs being equal to a number of weights for each associated perceptron. The technique also includes associating the TCAM with an array of x-bit saturating counters, and performing a branch prediction for a history vector of a given branch, the branch prediction indicating a perceptron prediction. The technique includes determining a most influential bit location in the history vector, the most influential bit location having a greatest weight of an associated perceptron.
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公开(公告)号：US20170344373A1
公开(公告)日：2017-11-30
申请号：US15440383
申请日：2017-02-23
CPC分类号： G06F9/30058 , G06F9/30021 , G06F9/30054 , G06F9/30134 , G06F9/30145 , G06F9/324 , G06F9/34 , G06F9/3806
摘要： Examples of techniques for distance-based branch prediction are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes: determining, by a processing system, a potential return instruction address (IA) by determining whether a relationship is satisfied between a first target IA and a first branch IA; storing a second branch IA as a return when a target IA of a second branch matches a potential return IA for the second branch; and applying the potential return IA for the second branch as a predicted target IA of a predicted branch IA stored as a return
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公开(公告)号：US20170212824A1
公开(公告)日：2017-07-27
申请号：US15003205
申请日：2016-01-21
发明人： EMRAH ACAR , JANE H. BARTIK , ALPER BUYUKTOSUNOGLU , BRIAN R. PRASKY , VIJAYALAKSHMI SRINIVASAN , JOHN-DAVID WELLMAN
CPC分类号： G06F11/3447 , G06F9/466 , G06F9/4887 , G06F11/3017 , G06F2201/88
摘要： The disclosed herein relates to a method of dynamic simultaneous multithreading metering for a plurality of independent threads being multithreaded. The method is executable by a processor. The method includes collecting attributes from processor and building a model utilizing the attributes. The method also includes performing the dynamic simultaneous multithreading metering in accordance with the model to output metering estimates for a first thread of the plurality of independent threads being multithreaded and updating the model based on the metering estimates.
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公开(公告)号：US20170206084A1
公开(公告)日：2017-07-20
申请号：US14995588
申请日：2016-01-14
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F5/00 , G06F7/584 , G06F9/30032 , G06F9/30098 , G06F9/30101 , G06F9/30134
摘要： A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.
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