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    POWER-DRIVEN SYNTHESIS UNDER LATENCY CONSTRAINTS
    3.
    发明申请
    POWER-DRIVEN SYNTHESIS UNDER LATENCY CONSTRAINTS 审中-公开
    功率驱动合成在LATENCY约束下

    公开(公告)号：US20160132765A1

    公开(公告)日：2016-05-12

    申请号：US14537857

    申请日：2014-11-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC: G06N3/04 ,  G06F1/28 ,  G06N3/063

    CPC classification number: G06N3/063 ,  G06F1/3243 ,  G06N3/049 ,  Y02D10/152

    Abstract: Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.

    Abstract translation: 本发明的实施例涉及在多核神经突触网络中满足等待时间限制。 在本发明的一个实施例中，提供了一种用于等待时间约束下的功率合成的方法和计算机程序产品。 神经突触网络的功耗被建模为线长度。 神经突触网络包括多个神经突触核。 多个神经突触核中的每一个被建模为放置图中的节点。 该图具有多个边。 基于尖峰频率将权重分配给多个边缘中的每一个。 确定神经突触核的布置。 该装置包括多个边缘中的每一个的长度。 将最大长度与多个边缘中的每一个的长度进行比较。 多个边缘中的至少一个边缘的重量在长度大于最大长度的情况下增加。

    Boundary latch and logic placement to satisfy timing constraints
    4.
    发明授权
    Boundary latch and logic placement to satisfy timing constraints 有权
    边界锁存和逻辑放置以满足时序约束

    公开(公告)号：US09098669B1

    公开(公告)日：2015-08-04

    申请号：US14152847

    申请日：2014-01-10

    Applicant: International Business Machines Corporation

    Inventor： Charles J. Alpert ,  Mark D. Aubel ,  Gregory F. Ford ,  Zhuo Li ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/08 ,  G06F2217/84

    Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.

    Abstract translation: 通过在电路中指定边界锁存器的子集，并将边界锁存器应用放置约束，便于集成电路设计中的边界时序。 在保持边界锁定位置约束的同时执行全局放置，并且在实施定时断言之后执行定时驱动放置。 使用深度优先搜索来指定边界锁存器，以沿着具有PI / PO的互连路径识别第一锁存器，并且根据设计者规则滤除不合格的锁存器。 如果它是由主输入驱动的锁存器的大簇或驱动主输出（如果它驱动太多的PO）或是馈通锁存器，则滤波器可被滤除。 约束包括边界锁存器和其他边界固定对象之间的移动，预置位或吸引力，即固定门或PI / PO。

    Structured placement of latches/flip-flops to minimize clock power in high-performance designs
    5.
    发明授权
    Structured placement of latches/flip-flops to minimize clock power in high-performance designs 有权
    锁存器/触发器的结构化放置，以最大限度地减少高性能设计中的时钟功率

    公开(公告)号：US08954912B2

    公开(公告)日：2015-02-10

    申请号：US13689437

    申请日：2012-11-29

    Applicant: International Business Machines Corporation

    Inventor： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.

    Abstract translation: 闩锁放置工具从初步布局（或基于网表）确定锁定器簇的形状，包括形状的纵横比，并且生成用于根据形状放置闩锁的模板。 锁存器基于锁存器大小被放置在本地时钟缓冲器（LCB）周围，从最大锁存器首先到最小锁存器，并且基于给定目标宽高比的理想位置。 理想的位置可以进一步基于LCB的时钟驱动器引脚配置。 最终模板优选地具有大致等于簇的形状的纵横比的纵横比，但是锁定位置可能受到时钟路由拓扑的约束。 通过将其中一个锁存器与另一个锁存器交换以最小化设计的总线长度，可以进一步优化集群内的锁存器布局。

    FAULT-TOLERANT POWER-DRIVEN SYNTHESIS
    7.
    发明申请
    FAULT-TOLERANT POWER-DRIVEN SYNTHESIS 审中-公开

    公开(公告)号：US20200097833A1

    公开(公告)日：2020-03-26

    申请号：US16696968

    申请日：2019-11-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhou Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC: G06N3/10

    Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

    Fault-tolerant power-driven synthesis
    8.
    发明授权
    Fault-tolerant power-driven synthesis 有权

    公开(公告)号：US10552740B2

    公开(公告)日：2020-02-04

    申请号：US14537844

    申请日：2014-11-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC: G06N3/10

    Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

    Power-driven synthesis under latency constraints
    9.
    发明授权
    Power-driven synthesis under latency constraints 有权

    公开(公告)号：US10354183B2

    公开(公告)日：2019-07-16

    申请号：US14537857

    申请日：2014-11-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC: G06N7/02 ,  G06N7/04 ,  G06N7/06 ,  G06N7/08 ,  G06N3/063 ,  G06F1/3234 ,  G06N3/04

    Abstract: Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.

    POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS
    10.
    发明申请
    POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS 审中-公开
    POWER DRIVEN SYNAPTIC网络合成

    公开(公告)号：US20160132767A1

    公开(公告)日：2016-05-12

    申请号：US14537826

    申请日：2014-11-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC: G06N3/063 ,  G06N3/04 ,  G06F17/30

    Abstract: Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

    Abstract translation: 本发明的实施例涉及在多核神经突触网络中提供功率最小化。 在本发明的一个实施例中，提供了一种用于电源突触网络合成的方法和计算机程序产品。 神经突触网络的功耗被建模为线长度。 神经突触网络包括多个神经突触核。 通过最小化导线长度来确定突触核心的布置。

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