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公开(公告)号：US10679120B2
公开(公告)日：2020-06-09
申请号：US14537826
申请日：2014-11-10
发明人： Charles J. Alpert , Pallab Datta , Myron D. Flickner , Zhuo Li , Dharmendra S. Modha , Gi-Joon Nam
IPC分类号： G06N3/06 , G06N3/04 , G06F30/327 , G06N3/063 , G06F119/06
摘要： Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.
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公开(公告)号：US09047436B2
公开(公告)日：2015-06-02
申请号：US14085285
申请日：2013-11-20
发明人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Jia Wang , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077
摘要： A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion.
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公开(公告)号：US08775996B2
公开(公告)日：2014-07-08
申请号：US13680775
申请日：2012-11-19
发明人： Charles Jay Alpert , Joseph Nicolas Kozhaya , Zhuo Li , Joseph J. Palumbo , Haifeng Qian , Phillip John Restle , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F17/5036 , G06F2217/62
摘要： A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.
摘要翻译： 具有直流（DC）变换分析单元的设计工具确定时钟网络设计的扇区内扇区缓冲器的候选接收器位置的组合。 对于每个候选接收器位置的组合，设计工具将候选接收器位置的组合的扇区的电阻转换成电路的电阻。 设计工具通过候选接收器位置的组合将电路的电容转换为电路的电流源。 该设计工具执行直流电路分析，其中直流电路分析的结果包括扇区节点处的电压方差和来自扇区对节点之间流动的电流的最大值。 设计工具确定候选接收器位置的哪一个组合具有电压的最小方差与直流电路分析的结果。
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公开(公告)号：US20140101629A1
公开(公告)日：2014-04-10
申请号：US14100553
申请日：2013-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译： 一些示例性实施例包括用于设计集成电路的计算机实现的方法。 计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。 计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个 输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。 计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。
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公开(公告)号：US08677299B1
公开(公告)日：2014-03-18
申请号：US13736648
申请日：2013-01-08
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译： 一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。 确定第一组多个群集锁存器中的多个组。 添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。 确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。 响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。
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公开(公告)号：US10552740B2
公开(公告)日：2020-02-04
申请号：US14537844
申请日：2014-11-10
发明人： Charles J. Alpert , Pallab Datta , Myron D. Flickner , Zhuo Li , Dharmendra S. Modha , Gi-Joon Nam
IPC分类号： G06N3/10
摘要： Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.
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公开(公告)号：US10354183B2
公开(公告)日：2019-07-16
申请号：US14537857
申请日：2014-11-10
发明人： Charles J. Alpert , Pallab Datta , Myron D. Flickner , Zhuo Li , Dharmendra S. Modha , Gi-Joon Nam
摘要： Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.
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公开(公告)号：US20160132767A1
公开(公告)日：2016-05-12
申请号：US14537826
申请日：2014-11-10
发明人： Charles J. Alpert , Pallab Datta , Myron D. Flickner , Zhuo Li , Dharmendra S. Modha , Gi-Joon Nam
摘要： Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.
摘要翻译： 本发明的实施例涉及在多核神经突触网络中提供功率最小化。 在本发明的一个实施例中，提供了一种用于电源突触网络合成的方法和计算机程序产品。 神经突触网络的功耗被建模为线长度。 神经突触网络包括多个神经突触核。 通过最小化导线长度来确定突触核心的布置。
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公开(公告)号：US09038009B2
公开(公告)日：2015-05-19
申请号：US14100553
申请日：2013-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
摘要翻译： 一些示例性实施例包括用于设计集成电路的计算机实现的方法。 计算机实现的方法包括接收集成电路的分层网络设计，其中分层设计包括耦合在一起的多个组件。 计算机实现的方法包括基于包括缺失断言，一个或多个缺失锁存器，源驱动程序中的至少一个的问题，检测组件数量的组件具有故障定时和不完整定时中的至少一个 输入源电压大于源极限极限阈值，以及具有大于漏极极限极限阈值的输入接收器的接收器。 计算机实现的方法包括使用独立于问题的不同组件替换组件，并且基于不同的组件测试组件数量的其他组件。
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10.发明申请公开(公告)号：US20150113491A1
公开(公告)日：2015-04-23
申请号：US14085285
申请日：2013-11-20
发明人： Charles J. Alpert , Zhuo Li , Chin Ngai Sze , Jia Wang , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077
摘要： A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion.
摘要翻译： 用于对集成电路拥塞和电线分配进行建模的基于计算机的系统和方法确定了与第一层组相对应的瓦片堵塞等于对应于第二层组的第一阻塞比的边界，形成分段线性公式， 将瓦块拥塞与二维瓦片的多个线材相关联，并且基于瓦片拥挤将多个线路的一部分分配到瓦片的一层。
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