公开(公告)号：US20040248363A1

公开(公告)日：2004-12-09

申请号：US10250157

申请日：2003-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karen A. Bard ,  David M. Dobuzinsky ,  Herbert L. Ho ,  Mahendar Kumar ,  Denise Pendleton ,  Michael D. Steigerwalt ,  Brian L. Walsh

IPC: H01L021/8242

CPC classification number: H01L29/66181 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/7841

Abstract: A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.

Abstract translation: 在整个阵列中延伸的具有均匀BOX层的SOI晶片中的DRAM阵列消除了处理中的环氧化物步骤; 将掩埋板与植入物连接，该植入物又连接到延伸穿过设备层的导电插塞和被偏置在地面上的盒子; 而通过晶体管是具有浮动体的平面NFET，其具有通过接地位线接地的泄漏放电路径。