公开(公告)号：US20040248363A1

公开(公告)日：2004-12-09

申请号：US10250157

申请日：2003-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karen A. Bard ,  David M. Dobuzinsky ,  Herbert L. Ho ,  Mahendar Kumar ,  Denise Pendleton ,  Michael D. Steigerwalt ,  Brian L. Walsh

IPC: H01L021/8242

CPC classification number: H01L29/66181 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/7841

Abstract: A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.

Abstract translation: 在整个阵列中延伸的具有均匀BOX层的SOI晶片中的DRAM阵列消除了处理中的环氧化物步骤; 将掩埋板与植入物连接，该植入物又连接到延伸穿过设备层的导电插塞和被偏置在地面上的盒子; 而通过晶体管是具有浮动体的平面NFET，其具有通过接地位线接地的泄漏放电路径。

公开(公告)号：US20020192888A1

公开(公告)日：2002-12-19

申请号：US10183336

申请日：2002-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

IPC: H01L021/336 ,  H01L021/8234

CPC classification number: H01L29/7834 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66628 ,  Y10S438/976

Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

Abstract translation: 本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。 具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。