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公开(公告)号:US20230252217A1
公开(公告)日:2023-08-10
申请号:US17650656
申请日:2022-02-10
发明人: Rongjian LIANG , Hua XIANG , Jinwook JUNG , Gi-Joon NAM , Lakshmi N. REDDY , Shyam RAMJI , Diwesh PANDEY , Gustavo Enrique TELLEZ
IPC分类号: G06F30/398 , G06F30/394 , G06N3/08
CPC分类号: G06F30/398 , G06F30/394 , G06N3/08
摘要: Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.
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2.
公开(公告)号:US20230394211A1
公开(公告)日:2023-12-07
申请号:US17805198
申请日:2022-06-02
发明人: Jinwook JUNG , Gi-Joon NAM , Jennifer KAZDA , Gustavo Enrique TELLEZ , Chau-Chin HUANG , Yao-Wen CHENG
IPC分类号: G06F30/3315 , G06F30/327
CPC分类号: G06F30/3315 , G06F30/327 , G06F2119/18
摘要: Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program (“ILP”) operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.
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公开(公告)号:US20230306179A1
公开(公告)日:2023-09-28
申请号:US17656364
申请日:2022-03-24
发明人: Hua XIANG , Benjamin Neil TROMBLEY , Gi-Joon NAM , Gustavo Enrique TELLEZ , Paul G. VILLARRUBIA
IPC分类号: G06F30/3953
CPC分类号: G06F30/3953
摘要: Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.
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