公开(公告)号：US20230385496A1

公开(公告)日：2023-11-30

申请号：US17664861

申请日：2022-05-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jinwook JUNG ,  Jennifer KAZDA ,  Schuyler ELDRIDGE ,  Peilin SONG ,  Gi-Joon NAM

IPC分类号： G06F30/3315 ,  G06F21/75

CPC分类号： G06F30/3315 ,  G06F21/75 ,  G06F2117/04

摘要： Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.

公开(公告)号：US20230252217A1

公开(公告)日：2023-08-10

申请号：US17650656

申请日：2022-02-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Rongjian LIANG ,  Hua XIANG ,  Jinwook JUNG ,  Gi-Joon NAM ,  Lakshmi N. REDDY ,  Shyam RAMJI ,  Diwesh PANDEY ,  Gustavo Enrique TELLEZ

IPC分类号： G06F30/398 ,  G06F30/394 ,  G06N3/08

CPC分类号： G06F30/398 ,  G06F30/394 ,  G06N3/08

摘要： Design rule violations (“DRVs”) may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

公开(公告)号：US20240184963A1

公开(公告)日：2024-06-06

申请号：US18061368

申请日：2022-12-02

申请人： International Business Machines Corporation

发明人： Victor N. KRAVETS ,  Gi-Joon NAM ,  Alexey Y. LVOV ,  Ashish JAITLY

IPC分类号： G06F30/33

CPC分类号： G06F30/33

摘要： A method includes receiving a circuit design and a specification for the circuit design and determining a first hypothesized change to the circuit design. Making the first hypothesized change to the circuit design produces a first changed circuit design. The method also includes determining a first counterexample input that causes the first changed circuit design to produce an output that departs from the specification and determining a second hypothesized change to the circuit design based at least in part on the first hypothesized change. Making the second hypothesized change to the circuit design produces a second changed circuit design. The method further includes, in response to determining that the second changed circuit design has no counterexample input that causes the second changed circuit design to produce an output that departs from the specification, making the second hypothesized change to the circuit design.

公开(公告)号：US20230237233A1

公开(公告)日：2023-07-27

申请号：US17649180

申请日：2022-01-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hua XIANG ,  Benjamin Neil TROMBLEY ,  Gi-Joon NAM ,  Gustavo E. TELLEZ ,  Paul G. VILLARRUBIA

IPC分类号： G06F30/392

CPC分类号： G06F30/392

摘要： Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

公开(公告)号：US20230394211A1

公开(公告)日：2023-12-07

申请号：US17805198

申请日：2022-06-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jinwook JUNG ,  Gi-Joon NAM ,  Jennifer KAZDA ,  Gustavo Enrique TELLEZ ,  Chau-Chin HUANG ,  Yao-Wen CHENG

IPC分类号： G06F30/3315 ,  G06F30/327

CPC分类号： G06F30/3315 ,  G06F30/327 ,  G06F2119/18

摘要： Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program (“ILP”) operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.

公开(公告)号：US20230385503A1

公开(公告)日：2023-11-30

申请号：US17804070

申请日：2022-05-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Alexey Y LVOV ,  Gi-Joon NAM ,  Benjamin Neil TROMBLEY ,  Lakshmi N REDDY ,  Paul G VILLARRUBIA

IPC分类号： G06F30/392 ,  G06F30/27

CPC分类号： G06F30/392 ,  G06F30/27

摘要： Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.

公开(公告)号：US20230306179A1

公开(公告)日：2023-09-28

申请号：US17656364

申请日：2022-03-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hua XIANG ,  Benjamin Neil TROMBLEY ,  Gi-Joon NAM ,  Gustavo Enrique TELLEZ ,  Paul G. VILLARRUBIA

IPC分类号： G06F30/3953

CPC分类号： G06F30/3953

摘要： Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.