公开(公告)号：US09601511B2

公开(公告)日：2017-03-21

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud Vinet ,  Kangguo Cheng ,  Bruce Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/223 ,  H01L21/265 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

公开(公告)号：US09252052B2

公开(公告)日：2016-02-02

申请号：US14096563

申请日：2013-12-04

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L29/00 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09059041B2

公开(公告)日：2015-06-16

申请号：US13933642

申请日：2013-07-02

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A l'Energie atomique et aux Energies alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

Abstract translation: 通过顶部半导体层和绝缘体上半导体（SOI）衬底的掩埋绝缘体层形成沟槽。 执行选择性外延以形成填充沟槽并与处理衬底的半导体材料外延对准的体半导体部分。 在顶部半导体层和体半导体部分上沉积至少一个电介质层，并且被图案化以在顶部半导体层和体半导体部分的选定区域上形成开口。 半导体合金材料直接在顶部半导体层和体半导体部分的物理暴露表面上沉积在开口内。 半导体合金材料在随后的退火中与下面的半导体材料混合。 在SOI区域和体区域的每一个内，根据半导体材料是否与半导体合金材料混合形成两种类型的半导体材料部分。

公开(公告)号：US20150008520A1

公开(公告)日：2015-01-08

申请号：US13933642

申请日：2013-07-02

Applicant: International Business Machines Corporation ,  Commissariat A I'Energie atomique et aux Energies alternatives ,  STMicroelectronics, Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

公开(公告)号：US20140099773A1

公开(公告)日：2014-04-10

申请号：US14096515

申请日：2013-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC.

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US20150279861A1

公开(公告)日：2015-10-01

申请号：US14739736

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A I'Energie atomique et aux Energies alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

Abstract translation: 通过顶部半导体层和绝缘体上半导体（SOI）衬底的掩埋绝缘体层形成沟槽。 执行选择性外延以形成填充沟槽并与处理衬底的半导体材料外延对准的体半导体部分。 在顶部半导体层和体半导体部分上沉积至少一个电介质层，并且被图案化以在顶部半导体层和体半导体部分的选定区域上形成开口。 半导体合金材料直接在顶部半导体层和体半导体部分的物理暴露表面上沉积在开口内。 半导体合金材料在随后的退火中与下面的半导体材料混合。 在SOI区域和体区域的每一个内，根据半导体材料是否与半导体合金材料混合形成两种类型的半导体材料部分。

公开(公告)号：US09105691B2

公开(公告)日：2015-08-11

申请号：US13859013

申请日：2013-04-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick C. Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/00 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76237 ,  H01L21/76897 ,  H01L21/84

Abstract: A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material.

Abstract translation: 一种形成绝缘体上半导体（SOI）器件的方法包括：在SOI衬底中限定浅沟槽隔离（STI）结构，所述SOI衬底包括体层，主体层上的埋层绝缘体（BOX）层，以及 BOX层上的SOI层; 在对应于STI结构的较低位置的本体层的一部分中形成掺杂区域，所述掺杂区域横向延伸到BOX层下面的体层中; 相对于本体层的未掺杂区域选择性地蚀刻本体层的掺杂区域，使得STI结构的较低位置切割BOX层; 并用绝缘体填充材料填充STI结构。

公开(公告)号：US08969966B2

公开(公告)日：2015-03-03

申请号：US13866077

申请日：2013-04-19

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。

公开(公告)号：US20140302661A1

公开(公告)日：2014-10-09

申请号：US13859013

申请日：2013-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick C. Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76237 ,  H01L21/76897 ,  H01L21/84

Abstract: A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material.

Abstract translation: 一种形成绝缘体上半导体（SOI）器件的方法包括：在SOI衬底中限定浅沟槽隔离（STI）结构，所述SOI衬底包括体层，主体层上的埋层绝缘体（BOX）层，以及 BOX层上的SOI层; 在对应于STI结构的较低位置的本体层的一部分中形成掺杂区域，所述掺杂区域横向延伸到BOX层下面的体层中; 相对于本体层的未掺杂区域选择性地蚀刻本体层的掺杂区域，使得STI结构的较低位置切割BOX层; 并用绝缘体填充材料填充STI结构。

公开(公告)号：US09293474B2

公开(公告)日：2016-03-22

申请号：US14739736

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A l'Energie atomique et aux Energies alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.