公开(公告)号：US20230074528A1

公开(公告)日：2023-03-09

申请号：US17468278

申请日：2021-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ali S. El-Zein ,  Wolfgang Roesner ,  Viresh Paruthi ,  Stephen Gerard Shuma ,  Stephen John Barnfield ,  Maya Safieddine ,  Benedikt Geukes ,  Klaus-Dieter Schubert ,  Gabor Drasny

IPC分类号： G06F30/327 ,  G06F30/3308

摘要： A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.

公开(公告)号：US20230072459A1

公开(公告)日：2023-03-09

申请号：US17464262

申请日：2021-09-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Gavin B. Meil ,  Kilaus-Dieter Schubert ,  Benedikt Geukes ,  Stephen John Barnfield ,  Maya Safieddine

IPC分类号： G06F30/396 ,  G06F1/26 ,  G06F1/06

摘要： A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.

公开(公告)号：US11907634B2

公开(公告)日：2024-02-20

申请号：US17464262

申请日：2021-09-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Gavin B. Meil ,  Kilaus-Dieter Schubert ,  Benedikt Geukes ,  Stephen John Barnfield ,  Maya Safieddine

IPC分类号： G06F1/06 ,  G06F1/26 ,  G06F30/396

CPC分类号： G06F30/396 ,  G06F1/06 ,  G06F1/26

摘要： A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.