公开(公告)号：US20230050432A1

公开(公告)日：2023-02-16

申请号：US17399397

申请日：2021-08-11

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Michael Stewart Gray ,  Mitchell R. DeHond

IPC: G06F30/392 ,  G06F30/398 ,  G03F1/70

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

公开(公告)号：US11941340B2

公开(公告)日：2024-03-26

申请号：US17402710

申请日：2021-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Alexander Bowen ,  Gerald L Strevig, III ,  Amanda Christine Venton ,  Robert Mahlon Averill, III ,  Adam P. Matheny ,  David Wolpert ,  Mitchell R. DeHond

IPC: G06F30/39 ,  G06F30/398

CPC classification number: G06F30/398

Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

公开(公告)号：US11822867B2

公开(公告)日：2023-11-21

申请号：US17401441

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Michael Stewart Gray ,  Mitchell R. DeHond

IPC: G06F30/398 ,  G06F115/12 ,  G06F113/18 ,  G06F111/04

CPC classification number: G06F30/398 ,  G06F2111/04 ,  G06F2113/18 ,  G06F2115/12

Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

公开(公告)号：US20170161425A1

公开(公告)日：2017-06-08

申请号：US14957700

申请日：2015-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mitchell R. DeHond ,  Ulrich A. Finkler ,  Harold E. Reindel ,  Steven E. Washburn ,  Richard Q. Williams

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: Methodologies for compact modeling of circuit layouts to accurately account for effects of layout-induced changes in semiconductor devices induced by various intentional and unintentional mechanisms present in semiconductor processes are disclosed. The layout-sensitive compact model accounts for the impact of large layout variation on circuits by implementing techniques for obtaining the correct layout-dependent response approximations and by incorporating layout extraction techniques to obtain correct geometric parameters that drive the LDE response. In particular, these techniques include utilizing shape sections for analyzing in detail various specific region shapes of the semiconductor device. The shape sections are defined by locating vertices of each region shape and rendering reference lines at each vertex. The shape section definitions are utilized in the compact model to determine device model quantities, such as induced LDE effects upon a transistor from the region, at a finer granularity to provide for more accurate simulations.

公开(公告)号：US12112114B2

公开(公告)日：2024-10-08

申请号：US17399397

申请日：2021-08-11

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Michael Stewart Gray ,  Mitchell R. DeHond

IPC: G06F30/30 ,  G03F1/70 ,  G06F30/392 ,  G06F30/398 ,  G06F111/20

CPC classification number: G06F30/392 ,  G03F1/70 ,  G06F30/398 ,  G06F2111/20

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

公开(公告)号：US20230051392A1

公开(公告)日：2023-02-16

申请号：US17402710

申请日：2021-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Alexander Bowen ,  Gerald L Strevig, III ,  Amanda Christine Venton ,  Robert Mahlon Averill, III ,  Adam P. Matheny ,  David Wolpert ,  Mitchell R. DeHond

IPC: G06F30/398

Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

公开(公告)号：US20230050539A1

公开(公告)日：2023-02-16

申请号：US17401441

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Michael Stewart Gray ,  Mitchell R. DeHond

IPC: G06F30/398

Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.