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公开(公告)号：US20240046132A1
公开(公告)日：2024-02-08
申请号：US17817549
申请日：2022-08-04
Applicant: International Business Machines Corporation
Inventor： Muir Kumph
CPC classification number: G06N10/40 , H01L39/223
Abstract: Techniques and couplers for managing coupling between qubits are presented. A coupler can be between, and connected to, a first qubit and second qubit. The coupler can comprise three Josephson junctions (JJs). The first and second JJs can be symmetrical, which facilitates creation of a first mode of oscillation and second mode of oscillation opposite of the first mode. Third JJ facilitates a division between the first and second modes. An activation status of a ZZ gate between the first and second qubits can be controlled based on excitation status of first mode and a relationship between first mode and second mode, the excitation status being based on whether a pulse is applied to the coupler. When no pulse is applied, ZZ gate is inactive and there is no coupling. When pulse is applied, first mode is in excited state activating ZZ gate, and there is a coupling between qubits.
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公开(公告)号：US20220180235A1
公开(公告)日：2022-06-09
申请号：US17111053
申请日：2020-12-03
Applicant: International Business Machines Corporation
Inventor： Muir Kumph , David C. Mckay , Oliver Dial
IPC: G06N10/00
Abstract: Techniques regarding qubit coupling structures that enable RIP gates are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a coupling structure coupled to a first qubit and a second qubit. The coupling structure can have a plurality of coupling pathways. A coupling pathway from the plurality of coupling pathways can be a resonator. Also, the first qubit can be coupled to a first end of the resonator, and the second qubit can be coupled to a point along a length of the resonator.
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公开(公告)号：US20210408112A1
公开(公告)日：2021-12-30
申请号：US16917016
申请日：2020-06-30
Applicant: International Business Machines Corporation
Inventor： Aaron Finck , John Blair , April Carniol , Oliver Dial , Muir Kumph
Abstract: Devices and/or computer-implemented methods to facilitate ZZ cancellation between qubits are provided. According to an embodiment, a device can comprise a coupler device that operates in a first oscillating mode and a second oscillating mode. The device can further comprise a first superconducting qubit coupled to the coupler device based on a first oscillating mode structure corresponding to the first oscillating mode and based on a second oscillating mode structure corresponding to the second oscillating mode. The device can further comprise a second superconducting qubit coupled to the coupler device based on the first oscillating mode structure and the second oscillating mode structure.
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公开(公告)号：US10924193B2
公开(公告)日：2021-02-16
申请号：US15721106
申请日：2017-09-29
Applicant: International Business Machines Corporation
Inventor： Mohit Kapur , Muir Kumph
Abstract: Embodiments include techniques for transmitting and receiving radio frequency (RF) signals, where the techniques for generating, via a digital analog converter (DAC), a frequency signal, and filtering the frequency signal to produce a first filtered signal and a second filtered signal. The techniques also include transmitting the second filtered signal to a device under test, and filtering the second filtered signal into a sub-signal having one or more components. The techniques include mixing the first filtered signal with the sub-signal to produce a first mixed signal, subsequently mixing the first mixed signal with an output signal received from the device under test to produce a second mixed signal, and converting the second mixed signal for analysis.
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公开(公告)号：US20190103927A1
公开(公告)日：2019-04-04
申请号：US15721106
申请日：2017-09-29
Applicant: International Business Machines Corporation
Inventor： Mohit Kapur , Muir Kumph
Abstract: Embodiments include techniques for transmitting and receiving radio frequency (RF) signals, where the techniques for generating, via a digital analog converter (DAC), a frequency signal, and filtering the frequency signal to produce a first filtered signal and a second filtered signal. The techniques also include transmitting the second filtered signal to a device under test, and filtering the second filtered signal into a sub-signal having one or more components. The techniques include mixing the first filtered signal with the sub-signal to produce a first mixed signal, subsequently mixing the first mixed signal with an output signal received from the device under test to produce a second mixed signal, and converting the second mixed signal for analysis.
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Patent Agency Ranking
公开(公告)号：US12249748B2
公开(公告)日：2025-03-11
申请号：US17935023
申请日：2022-09-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Muir Kumph , Oliver Dial , John Michael Cotte , David Abraham
Abstract: A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.
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公开(公告)号：US20240104414A1
公开(公告)日：2024-03-28
申请号：US17935023
申请日：2022-09-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Muir Kumph , Oliver Dial , John Michael Cotte , David Abraham
CPC classification number: G06N10/40 , H01R12/721 , H02J50/05
Abstract: A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.
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公开(公告)号：US20230359917A1
公开(公告)日：2023-11-09
申请号：US17740279
申请日：2022-05-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： David Abraham , John Michael Cotte , Muir Kumph
IPC: G06N10/40
CPC classification number: G06N10/40
Abstract: A quantum computing (QC) chip module includes an interposer chip having a footprint. A qubit chip bump is bonded to the interposer chip and arranged so that the qubit chip extends beyond the footprint of the interposer chip. The interposer chip extends beyond an edge of the qubit chip. A wiring harness is connected to the interposer chip.
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公开(公告)号：US11750175B2
公开(公告)日：2023-09-05
申请号：US17025642
申请日：2020-09-18
Applicant: International Business Machines Corporation
Inventor： Muir Kumph
Abstract: Techniques regarding quantum gate coupling are provided. For example, one or more embodiments described herein can comprise a method for driving multiple resonator induced phase gates from the same signal control line. The method can comprise controlling quantum gate coupling, via a quantum circuit, by filtering a resonator induced phase gate signal from a signal control line that is multiplexed with a plurality of resonator induced phase gate signals.
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公开(公告)号：US20200272196A1
公开(公告)日：2020-08-27
申请号：US15929628
申请日：2020-05-13
Applicant: International Business Machines Corporation
Inventor： Mohit Kapur , Muir Kumph , Jiri Stehlik
Abstract: An aspect includes a direct digital synthesis system including a waveform generator with a waveform memory operable to store a plurality of waveform vectors and output a selected waveform vector. The direct digital synthesis system also includes a digital-to-analog converter operable to convert the selected waveform vector from a digital value to an analog signal responsive to a reference clock. The direct digital synthesis system further includes a controller operable to maintain phase continuity of the analog signal when an output of the analog signal is interrupted and restored.
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