公开(公告)号：US12033981B2

公开(公告)日：2024-07-09

申请号：US17123350

申请日：2020-12-16

Applicant: International Business Machines Corporation

Inventor： David Abraham ,  Oliver Dial ,  John Michael Cotte ,  Kevin Shawn Petrarca

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/06 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/06 ,  H01L23/481 ,  H01L25/50 ,  H01L2225/06513

Abstract: A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

公开(公告)号：US20230230927A1

公开(公告)日：2023-07-20

申请号：US18192542

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： David Abraham ,  John Michael Cotte ,  Shawn Anthony Hall

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14

Abstract: A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

公开(公告)号：US20220059465A1

公开(公告)日：2022-02-24

申请号：US16998451

申请日：2020-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Abraham ,  John Michael Cotte ,  Shawn Anthony Hall

IPC: H01L23/538 ,  G06N10/00 ,  H01L23/00

Abstract: A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

公开(公告)号：US11908756B2

公开(公告)日：2024-02-20

申请号：US17644695

申请日：2021-12-16

Applicant: International Business Machines Corporation

Inventor： David Abraham ,  John Michael Cotte

IPC: H01L23/049 ,  H01L23/498 ,  H01L23/16 ,  H01L23/13 ,  H01L23/06 ,  H01L23/552 ,  H01L21/52

CPC classification number: H01L23/049 ,  H01L21/52 ,  H01L23/06 ,  H01L23/13 ,  H01L23/16 ,  H01L23/49888 ,  H01L23/552

Abstract: Techniques regarding qubit chip assemblies are provided. For example, one or more embodiments described herein can include an apparatus that can comprise a qubit chip positioned on an interposer chip. The apparatus can also comprise an electrical connector in direct contact with the interposer chip. The electrical connector can establish an electrical communication between a wire and a contact pad of the interposer chip that is coupled to the qubit chip.

公开(公告)号：US11676903B2

公开(公告)日：2023-06-13

申请号：US16998451

申请日：2020-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Abraham ,  John Michael Cotte ,  Shawn Anthony Hall

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14

Abstract: A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

公开(公告)号：US11411158B2

公开(公告)日：2022-08-09

申请号：US17130376

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Timothy Phung ,  David Abraham

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/04 ,  H01L39/24 ,  H01L39/22

Abstract: Techniques for creating an offset embedded ground plane cutout for a qubit device to facilitate frequency tuning of the qubit device are presented. A qubit device can comprise a first substrate and second substrate in a flip-chip assembly. The qubit chip assembly can comprise a qubit component fabricated on the first substrate. The qubit component can comprise a Josephson junction (JJ) circuit that can be offset from a center point of the qubit component. The qubit chip assembly can comprise an embedded ground plane situated on a surface of the qubit chip assembly. A cutout section can be formed in the ground plane and positioned over the JJ circuit. The cutout section can enable access of an optical signal or magnetic flux to the JJ circuit. A frequency of the qubit component can be tuned based on application of the optical signal or magnetic flux to the JJ circuit.

公开(公告)号：US20240230202A9

公开(公告)日：2024-07-11

申请号：US17445265

申请日：2021-08-17

Applicant: International Business Machines Corporation

Inventor： David Abraham ,  Gerard McVicker ,  Sri M. Sri-Jayantha ,  Vijayeshwar Das Khanna ,  Nicholas A. Masluk

IPC: F25D3/10 ,  H01P3/00

CPC classification number: F25D3/10 ,  H01P3/003

Abstract: A cryogenic system comprising a first cryogenic stage and a second cryogenic stage. A first signal line passing from the first cryogenic stage and is connected to a superconducting thermal break in the second cryogenic stage. A second signal line connecting the superconducting thermal break to a cryogenic device.

公开(公告)号：US20240133609A1

公开(公告)日：2024-04-25

申请号：US17445265

申请日：2021-08-16

Applicant: International Business Machines Corporation

Inventor： David Abraham ,  Gerard McVicker ,  Sri M. Sri-Jayantha ,  Vijayeshwar Das Khanna ,  Nicholas A. Masluk

IPC: F25D3/10 ,  H01P3/00

CPC classification number: F25D3/10 ,  H01P3/003

Abstract: A cryogenic system comprising a first cryogenic stage and a second cryogenic stage. A first signal line passing from the first cryogenic stage and is connected to a superconducting thermal break in the second cryogenic stage. A second signal line connecting the superconducting thermal break to a cryogenic device.

公开(公告)号：US20230363294A1

公开(公告)日：2023-11-09

申请号：US17861151

申请日：2022-07-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Abraham ,  John Michael Cotte ,  Nicholas A. Masluk

IPC: H01L39/04 ,  H01L39/24 ,  G06N10/40

CPC classification number: H01L39/04 ,  G06N10/40 ,  H01L39/24

Abstract: A cryogenic electronics device includes a semiconductor chip. A substrate is flip-chip bonded to the semiconductor chip. A plurality of bump bonds are concentrated in a bump region of the semiconductor chip. A plurality of circuit elements are arranged in a predefined region of the semiconductor chip. The predefined region and the bump region are separate regions.

公开(公告)号：US20230058897A1

公开(公告)日：2023-02-23

申请号：US17445248

申请日：2021-08-17

Applicant: International Business Machines Corporation

Inventor： David Abraham ,  Gerard McVicker ,  Sri M. Sri-Jayantha

IPC: H01L23/367

Abstract: Embodiments of a present invention disclose an apparatus including a silicon wafer and a through-silicon-via (TSV) filled with a thermally conductive material located in the silicon wafer, wherein the thermally conductive material has better thermal conduction properties than the silicon wafer when at cryogenic temperatures. A shunt layer connected to the thermal material in the TSV and a heat generating device located directly on top of the thermal material in the TSV and directly on top of the shunt layer, wherein the heat generated by the heat generating device is removed directly by the shunt layer and the thermal material in the TSV.