中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.013 seconds)

    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
    1.
    发明申请
    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
    形成增强板阵列隔离装置的结构和方法

    公开(公告)号：US20150279843A1

    公开(公告)日：2015-10-01

    申请号：US14736695

    申请日：2015-06-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    IPC: H01L27/108

    CPC classification number: H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

    Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

    Abstract translation: 提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。 电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。 保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

    Array and moat isolation structures and method of manufacture
    2.
    发明授权
    Array and moat isolation structures and method of manufacture 有权
    阵列和护城隔离结构及其制造方法

    公开(公告)号：US09240452B2

    公开(公告)日：2016-01-19

    申请号：US14149280

    申请日：2014-01-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Naoyoshi Kusaba ,  Oh-jung Kwon ,  Zhengwen Li ,  Hongwen Yan

    IPC: H01L29/06 ,  H01L29/423 ,  H01L27/108 ,  H01L29/66 ,  H01L29/94 ,  H01L21/762

    CPC classification number: H01L29/423 ,  H01L21/762 ,  H01L27/10805 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    Abstract: An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

    Abstract translation: 提供了具有异质深沟槽填充的eDRAM的阵列或护城河隔离结构和制造方法。 该方法包括形成用于存储器阵列的深沟槽和隔离区域。 该方法还包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。 该方法还包括用金属填充用于存储器阵列的深沟槽的剩余部分，并且用金属衬里隔离区域的深沟槽。 该方法还包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区的深沟槽的剩余部分。 该方法还包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。 存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

Patent Agency Ranking