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    DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP
    5.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP 有权
    动态随机访问存储器单元与自对准的条纹

    公开(公告)号：US20150206884A1

    公开(公告)日：2015-07-23

    申请号：US14158956

    申请日：2014-01-20

    申请人： International Business Machines Corporation

    发明人： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

    IPC分类号： H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/417

    CPC分类号： H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

    摘要： After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

    摘要翻译： 在形成用于存取晶体管的沟槽电容器以及源极和漏极区域和栅极结构之后，在每个源极区域的第一侧壁上形成介电隔离物，同时物理地暴露每个源极区域的第二侧壁和漏极区域的侧壁。 在去除沟槽顶部电介质部分期间，可以使用每个电介质间隔物作为蚀刻掩模，以形成用于形成带状结构的带状空腔。 可选地，可以进行半导体材料的选择性沉积以形成凸起的源极和漏极区域。 在这种情况下，升高的源极区域仅从第一侧壁生长并且不从第二侧壁生长。 凸起的源极区域可以在形成带状空腔期间用作蚀刻掩模的一部分。 带状结构形成为通过电介质间隔物与相邻的存取晶体管电隔离的自对准结构。

    Dynamic random access memory cell employing trenches located between lengthwise edges of semiconductor fins
    8.
    发明授权
    Dynamic random access memory cell employing trenches located between lengthwise edges of semiconductor fins 有权
    动态随机存取存储器单元采用位于半导体鳍片纵向边缘之间的沟槽

    公开(公告)号：US09337200B2

    公开(公告)日：2016-05-10

    申请号：US14087819

    申请日：2013-11-22

    申请人： International Business Machines Corporation

    发明人： Herbert L. Ho ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

    IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L29/417 ,  H01L21/762 ,  H01L29/66 ,  H01L29/94

    CPC分类号： H01L27/10867 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/66181 ,  H01L29/945

    摘要： After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.

    摘要翻译： 在体半导体衬底的上部形成半导体鳍片之后，形成浅沟槽隔离层，其包括电介质材料并且横向围绕每个半导体鳍片的下部。 沟槽形成在相邻的半导体鳍片对的纵向侧壁之间。 横向围绕每个沟槽的浅沟槽隔离层的部分提供了掩埋板和存取晶体管之间的电隔离。 可以通过蚀刻覆盖每个沟槽的一部分和对应的存取晶体管的源极区域的通孔，并且用导电材料填充通孔腔来形成带结构。 沟槽顶部氧化物结构将每个沟槽电容器的内部电极与用于接入鳍场效应晶体管的上覆栅极线电隔离。

    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
    9.
    发明申请
    STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
    形成增强板阵列隔离装置的结构和方法

    公开(公告)号：US20150279843A1

    公开(公告)日：2015-10-01

    申请号：US14736695

    申请日：2015-06-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

    摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

    摘要翻译： 提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。 电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。 保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

    STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION
    10.
    发明申请
    STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION 审中-公开
    结构和工艺分解深层电容电容器和隔离层

    公开(公告)号：US20150214244A1

    公开(公告)日：2015-07-30

    申请号：US14166155

    申请日：2014-01-28

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Herbert L. Ho ,  Sivananda K. Kanakasabapathy ,  Rishikesh Krishnan ,  Kern Rim

    IPC分类号： H01L27/12 ,  H01L27/08 ,  H01L21/324 ,  H01L21/306 ,  H01L21/762 ,  H01L49/02 ,  H01L27/02

    CPC分类号： H01L27/1203 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/90

    摘要： Formation of deep trench capacitors and isolation structures are decoupled by completing the isolation structures prior to etching trenches for capacitors and forming capacitors therein or vice-versa. Such decoupling of the formation of these respective structures allows different materials to be used in the deep trench capacitors and the isolation structures such as use of low permeability or dielectric constant materials and/or low Young's modulus materials in isolation structures to provide reduced AC capacitive coupling across isolation structures and/or relief of stresses associated with use of high dielectric constant materials or metal-insulator-metal (MIM) structures in deep trench capacitors. Such decoupling also allows increased efficiency of use of reaction chambers for the deep trench capacitors and the isolation structures.

    摘要翻译： 深沟槽电容器和隔离结构的形成通过在蚀刻用于电容器的沟槽和在其中形成电容器之前完成隔离结构来解耦，反之亦然。 这些相应结构的形成的这种解耦允许在深沟槽电容器和隔离结构中使用不同的材料，例如在隔离结构中使用低导磁率或介电常数材料和/或低杨氏模量材料来提供减小的AC电容耦合 跨越隔离结构和/或释放与在深沟槽电容器中使用高介电常数材料或金属 - 绝缘体 - 金属（MIM）结构有关的应力。 这种去耦还允许增加用于深沟槽电容器和隔离结构的反应室的使用效率。