公开(公告)号：US20180226511A1

公开(公告)日：2018-08-09

申请号：US15945937

申请日：2018-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/24 ,  H01L27/146 ,  H01L29/66

Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

公开(公告)号：US20180068994A1

公开(公告)日：2018-03-08

申请号：US15802541

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09911652B1

公开(公告)日：2018-03-06

申请号：US15472745

申请日：2017-03-29

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/5226 ,  H01L23/528

Abstract: Mandrel lines non-mandrel lines, and spacers are located in a structure having several layers. A spacer in the set of spacers comprises a structure formed above the top mask layer. A first trench is etched at a first location on a mandrel line through the top mask layer and stopping at the middle mask layer. A second trench is etched at a second location on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from the etching the trenches. Vias are formed in the first and second trenches. An air-gap is formed at a location of the spacer. The first via structure and a first portion of the bottom mask layer under the first via structure are removed and filled with a conductive metal.

公开(公告)号：US20170162554A1

公开(公告)日：2017-06-08

申请号：US14956834

申请日：2015-12-02

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20160266950A1

公开(公告)日：2016-09-15

申请号：US15161462

申请日：2016-05-23

Applicant: International Business Machines Corporation

Inventor： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/008 ,  G06F11/079 ,  G06F17/5009 ,  G06F17/5022 ,  G06F2217/10

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

Abstract translation: 提供了一种用于重用采样的机制，用于有效地进行细胞故障率估计过程变化和其他设计考虑。 首先，该机制对电路参数进行搜索，以确定相对于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样。 混合重要性抽样（MIS）有效地估计单个故障区域。 然后，该机制找到每个度量的重心，并发现重要性样本。 然后，对于对应于过程变化或其他设计考虑的每个新的原点，机制找到合适的投影并重新计算新的重要性抽样（IS）比率。

公开(公告)号：US20160126249A1

公开(公告)日：2016-05-05

申请号：US14527256

申请日：2014-10-29

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/115 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/408 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

Abstract translation: 从底部到顶部包含第一导电类型的非掺杂半导体部分和第二掺杂半导体部分的多个鳍结构从第一导电类型的第一掺杂半导体部分的表面向上延伸。 捕获材料（例如，电子捕获材料）沿着每个非掺杂半导体部分的侧壁表面的底部部分和每个第一掺杂半导体部分的暴露部分存在。 功能门结构跨越每个翅片结构。 金属线位于每个鳍结构上方并跨越每个功能门结构。 每个金属线垂直于每个功能栅极结构定向，并且具有与每个第二掺杂半导体部分的最顶表面的一部分直接物理接触的最底部表面。

公开(公告)号：US09324793B2

公开(公告)日：2016-04-26

申请号：US14871157

申请日：2015-09-30

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Edem Wornyo ,  Yiheng Xu ,  John Zhang

IPC: H01L21/461 ,  H01L23/58 ,  H01L29/06 ,  H01L29/66 ,  H01L51/05

CPC classification number: H01L29/0661 ,  H01L21/02071 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66621 ,  H01L29/66795 ,  H01L51/0525

Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

公开(公告)号：US20150279843A1

公开(公告)日：2015-10-01

申请号：US14736695

申请日：2015-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract translation: 提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。 电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。 保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

公开(公告)号：US09089080B2

公开(公告)日：2015-07-21

申请号：US13912591

申请日：2013-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC: H01L21/311 ,  H05K3/40 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01B17/66

CPC classification number: H05K3/40 ,  H01B17/66 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76822 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T156/1039 ,  Y10T156/1082 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24537 ,  Y10T428/24612 ,  Y10T428/24711 ,  H01L2924/00

Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.

Abstract translation: 包含在互连叠层中具有纳米级波纹界面的界面的介电复合结构提供了增强的粘合强度和界面断裂韧性。 还描述了进一步包含波纹粘合促进剂层以进一步增加本征界面粘合性的复合结构。 还描述了使用自组装聚合物体系和图案转移方法形成纳米级波纹界面以实现这些结构的方法。

公开(公告)号：US09087784B2

公开(公告)日：2015-07-21

申请号：US14167532

申请日：2014-01-29

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.

Abstract translation: 提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。 等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。