公开(公告)号：US20140327469A1

公开(公告)日：2014-11-06

申请号：US14028880

申请日：2013-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dirk PFEIFFER ,  Jean-Olivier PLOUCHART ,  Peilin SONG

IPC: H03K19/003

CPC classification number: H03K19/003

Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements that are arranged in series, where the first subset of PUF elements is arranged in parallel with respect to the second subset of PUF elements. In addition, the PUF system is measured to obtain at least one differential of states between the first subset of PUF elements and the second subset of PUF elements. Further, the method includes outputting an authentication sequence for the circuit that is based on the one or more differentials of states.

Abstract translation: 公开了使用物理不可克隆功能（PUF）的芯片认证相关的方法，系统和设备。 根据一种这样的方法，将测试电压施加到包括串联布置的PUF元件的第一子集和串联布置的PUF元件的第二子集的PUF系统，其中PUF元件的第一子集被布置在 相对于PUF元件的第二子集平行。 此外，测量PUF系统以获得PUF元素的第一子集和PUF元素的第二子集之间的状态的至少一个差异。 此外，该方法包括输出基于一个或多个状态差分的电路的认证序列。

公开(公告)号：US20230385496A1

公开(公告)日：2023-11-30

申请号：US17664861

申请日：2022-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jinwook JUNG ,  Jennifer KAZDA ,  Schuyler ELDRIDGE ,  Peilin SONG ,  Gi-Joon NAM

IPC: G06F30/3315 ,  G06F21/75

CPC classification number: G06F30/3315 ,  G06F21/75 ,  G06F2117/04

Abstract: Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.