公开(公告)号：US20240013050A1

公开(公告)日：2024-01-11

申请号：US17857593

申请日：2022-07-05

Applicant: International Business Machines Corporation

Inventor： Subhankar PAL ,  Alper BUYUKTOSUNOGLU ,  Ehud AHARONI ,  Nir DRUCKER ,  Omri SOCEANU ,  Hayim SHAUL ,  Kanthi SARPATWAR ,  Roman VACULIN ,  Moran BARUCH ,  Pradip BOSE

IPC: G06N3/08 ,  G06N3/063 ,  H04L9/00

CPC classification number: G06N3/082 ,  G06N3/063 ,  H04L9/008

Abstract: An example system includes a processor to prune a machine learning model based on an importance of neurons or weights. The processor is to further permute and pack remaining neurons or weights of the pruned machine learning model to reduce an amount of ciphertext computation under a selected constraint.

公开(公告)号：US20230012710A1

公开(公告)日：2023-01-19

申请号：US17305784

申请日：2021-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aporva AMARNATH ,  Augusto VEGA ,  Alper BUYUKTOSUNOGLU ,  Hubertus FRANKE ,  John-David WELLMAN ,  Pradip BOSE

IPC: G06F9/48 ,  G06F9/445 ,  G06N20/00

Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

公开(公告)号：US20170308147A1

公开(公告)日：2017-10-26

申请号：US15605154

申请日：2017-05-25

Applicant: International Business Machines Corporation

Inventor： Pradip BOSE ,  Alper BUYUKTOSUNOGLU ,  Hubertus FRANKE ,  Priyanka TEMBEY ,  Dilma M. DA SILVA

IPC: G06F1/32 ,  G06F9/50 ,  G06F1/26 ,  G06F9/48

CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/50 ,  Y02D10/24

Abstract: Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

公开(公告)号：US20230222279A1

公开(公告)日：2023-07-13

申请号：US17647679

申请日：2022-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik V SWAMINATHAN ,  Alper BUYUKTOSUNOGLU ,  Pradip BOSE ,  Bulent ABALI

IPC: G06F30/398 ,  H03M13/27 ,  G06F30/392

CPC classification number: G06F30/398 ,  H03M13/27 ,  G06F30/392 ,  G06F2119/12

Abstract: Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes (“ECC”) and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

公开(公告)号：US20210303306A1

公开(公告)日：2021-09-30

申请号：US16836794

申请日：2020-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alper BUYUKTOSUNOGLU ,  David TRILLA RODRIGUEZ ,  John-David WELLMAN ,  Pradip BOSE

IPC: G06F9/30 ,  G06F9/32

Abstract: Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.

公开(公告)号：US20210208992A1

公开(公告)日：2021-07-08

申请号：US16736959

申请日：2020-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Augusto VEGA ,  Alper BUYUKTOSUNOGLU ,  Pradip BOSE

IPC: G06F11/34 ,  H04L29/08 ,  G06N5/04 ,  G06N20/00

Abstract: Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.

公开(公告)号：US20200319994A1

公开(公告)日：2020-10-08

申请号：US16375751

申请日：2019-04-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alper BUYUKTOSUNOGLU ,  Ramon BERTRAN MONFORT ,  Calvin BULLA ,  Pradip BOSE ,  Hubertus FRANKE

IPC: G06F11/36

Abstract: Embodiments for generating representative microbenchmarks in a computing environment are provided. One or more tracing points may be selected in a target application. Executed instructions and used data of the target application may be dynamically traced according to the one or more tracing points according to a tracing plan. Tracing information of the dynamic tracing may be replicated in an actual computing environment and a simulated computing environment.