公开(公告)号：US20230041702A1

公开(公告)日：2023-02-09

申请号：US17394173

申请日：2021-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DEREK E. WILLIAMS ,  GUY L. GUTHRIE ,  Bernard C. Drerup ,  Hugh Shen ,  Alexander Michael Taft ,  Luke Murray ,  Richard Nicholas

IPC: G06F12/0811 ,  G06F12/121 ,  G06F30/32

Abstract: A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

公开(公告)号：US11561901B1

公开(公告)日：2023-01-24

申请号：US17394173

申请日：2021-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Bernard C. Drerup ,  Hugh Shen ,  Alexander Michael Taft ,  Luke Murray ,  Richard Nicholas

IPC: G06F12/0811 ,  G06F30/32 ,  G06F12/121

Abstract: A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

公开(公告)号：US09208027B2

公开(公告)日：2015-12-08

申请号：US14540356

申请日：2014-11-13

Applicant: International Business Machines Corporation

Inventor： Richard Nicholas

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/05

CPC classification number: G06F11/1076 ,  G06F11/1016 ,  H03M13/05

Abstract: Address error detection including a method that receives a read address corresponding to a read location in a memory. Data is read from the read location in the memory. The data is transformed at a computer based on the data and the read address to produce read data. Error correction codes (ECC) bits associated the read data are read from the read location in the memory. The ECC bits were generated based on the write data. It is determined whether the read data has an address error responsive to the read data and the ECC bits associated with the write data. An error is generated in response to determining that the read address has an address error.

Abstract translation: 地址错误检测，包括接收与存储器中的读取位置对应的读取地址的方法。 从存储器中的读取位置读取数据。 数据在计算机基于数据和读取地址进行变换以产生读取数据。 从存储器中的读取位置读取与读取数据相关联的纠错码（ECC）位。 基于写入数据生成ECC位。 确定读取数据是否具有响应于读取数据的地址错误和与写入数据相关联的ECC位。 响应于确定读地址具有地址错误而产生错误。

公开(公告)号：US20150074495A1

公开(公告)日：2015-03-12

申请号：US14540356

申请日：2014-11-13

Applicant: International Business Machines Corporation

Inventor： Richard Nicholas

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1016 ,  H03M13/05

Abstract: Address error detection including a method that receives a read address corresponding to a read location in a memory. Data is read from the read location in the memory. The data is transformed at a computer based on the data and the read address to produce read data. Error correction codes (ECC) bits associated the read data are read from the read location in the memory. The ECC bits were generated based on the write data. It is determined whether the read data has an address error responsive to the read data and the ECC bits associated with the write data. An error is generated in response to determining that the read address has an address error.

Abstract translation: 地址错误检测，包括接收与存储器中的读取位置对应的读取地址的方法。 从存储器中的读取位置读取数据。 数据在计算机基于数据和读取地址进行变换以产生读取数据。 从存储器中的读取位置读取与读取数据相关联的纠错码（ECC）位。 基于写入数据生成ECC位。 确定读取数据是否具有响应于读取数据的地址错误和与写入数据相关联的ECC位。 响应于确定读地址具有地址错误而产生错误。

公开(公告)号：US09170639B2

公开(公告)日：2015-10-27

申请号：US13859101

申请日：2013-04-09

Applicant: International Business Machines Corporation

Inventor： Joab D. Henderson ,  Richard Nicholas ,  Stephen J. Powell ,  Kenneth L. Wright

IPC: G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3275 ,  G06F11/073 ,  Y02D10/13 ,  Y02D10/14

Abstract: An approach for saving power in a memory subsystem that uses memory access idle timer to enable low power mode and memory scrub operation within computing system has been provided. The computing system determines that a memory subsystem is switched out of low power operation mode due to a memory scrub operation. In addition, the computing system bypasses the low power operation mode of an idle timer of the memory subsystem such that the memory subsystem is returned to the low power operation mode upon completion of the memory scrub operation. The computing system further sets a scrub flag of the memory subsystem to a high state, and clears the scrub flag to a low state to track if the idle timer should be bypassed.

Abstract translation: 已经提供了一种用于在使用存储器访问空闲定时器来实现计算系统内的低功率模式和存储器擦除操作的存储器子系统中节省功率的方法。 由于存储器擦除操作，计算系统确定存储器子系统从低功率操作模式切换。 此外，计算系统绕过存储器子系统的空闲定时器的低功率操作模式，使得存储器子系统在完成存储器擦除操作时返回到低功率操作模式。 计算系统还将存储器子系统的擦除标志设置为高状态，并将擦除标志清除为低状态，以跟踪是否应绕过空闲计时器。