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    Cache snooping mode extending coherence protection for certain requests
    1.
    发明授权
    Cache snooping mode extending coherence protection for certain requests 有权

    公开(公告)号：US11157409B2

    公开(公告)日：2021-10-26

    申请号：US16717868

    申请日：2019-12-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Luke Murray

    IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0891 ,  G06F12/0842

    Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.

    Initiating interconnect operation without waiting on lower level cache directory lookup
    4.
    发明授权
    Initiating interconnect operation without waiting on lower level cache directory lookup 有权

    公开(公告)号：US11163700B1

    公开(公告)日：2021-11-02

    申请号：US16862785

    申请日：2020-04-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Luke Murray

    IPC: G06F12/128

    Abstract: An upper level cache receives from an associated processor core a plurality of memory access requests including at least first and second memory access requests of differing first and second classes. Based on class histories associated with the first and second classes of memory access requests, the upper level cache initiates, on the system interconnect fabric, a first interconnect transaction corresponding to the first memory access request without first issuing the first memory access request to the lower level cache via a private communication channel between the upper level cache and the lower level cache. The upper level cache initiates, on the system interconnect fabric, a second interconnect transaction corresponding to the second memory access request only after first issuing the second memory access request to the lower level cache via the private communication channel between the upper level cache and the lower level cache and receiving a response to the second memory access request from the lower level cache.

    Gathering translation entry invalidation requests in a data processing system
    5.
    发明授权
    Gathering translation entry invalidation requests in a data processing system 有权

    公开(公告)号：US11693788B1

    公开(公告)日：2023-07-04

    申请号：US17834505

    申请日：2022-06-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Luke Murray ,  Hugh Shen

    IPC: G06F12/1045 ,  G06F12/0811 ,  G06F12/1027

    CPC classification number: G06F12/1045 ,  G06F12/0811 ,  G06F12/1027 ,  G06F2212/681

    Abstract: An arbiter gathers translation invalidation requests assigned to state machines of a lower-level cache into a set for joint handling in a processor core. The gathering includes selection of one of the set of gathered translation invalidation requests as an end-of-sequence (EOS) request. The arbiter issues to the processor core a sequence of the gathered translation invalidation requests terminating with the EOS request. Based on receipt of each of the gathered requests, the processor core invalidates any translation entries providing translation for the addresses specified by the translation invalidation requests and marks memory-referent requests dependent on the invalidated translation entries. Based on receipt of the EOS request and in response to all of the marked memory-referent requests draining from the processor core, the processor core issues a completion request to the lower-level cache indicating completion of servicing by the processor core of the set of gathered translation invalidation requests.

    Centralized distribution of multicast requests in a data processing system
    9.
    发明授权
    Centralized distribution of multicast requests in a data processing system 有权

    公开(公告)号：US12056050B2

    公开(公告)日：2024-08-06

    申请号：US18086501

    申请日：2022-12-21

    Applicant: International Business Machines Corporation

    Inventor： Derek E. Williams ,  Luke Murray ,  Guy L. Guthrie ,  Hugh Shen

    IPC: G06F12/0802 ,  G06F9/54 ,  G06F12/10

    CPC classification number: G06F12/0802 ,  G06F9/542 ,  G06F12/10 ,  G06F2212/603

    Abstract: A data processing system includes a master, a central request agent, and a plurality of snoopers communicatively coupled to a system fabric for communicating requests subject to retry. The master issues on the system fabric a multicast request intended for the plurality of snoopers. The central request agent receives the multicast request on the system fabric, assigns the multicast request to a particular state machine among a plurality of state machines in the central request agent, and provides the master a coherence response indicating successful completion of the multicast request. The central request agent repetitively issues on the system fabric a multicast request in association with a machine identifier identifying the particular state machine until a coherence response indicates the multicast request is successfully received by all of the plurality of snoopers.

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