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    Completion logic performing early commitment of a store-conditional access based on a flag
    1.
    发明授权
    Completion logic performing early commitment of a store-conditional access based on a flag 有权

    公开(公告)号：US11281582B2

    公开(公告)日：2022-03-22

    申请号：US16742380

    申请日：2020-01-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  William J. Starke ,  Hugh Shen

    IPC: G06F12/0815

    Abstract: A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.

    Cache snooping mode extending coherence protection for certain requests
    2.
    发明授权
    Cache snooping mode extending coherence protection for certain requests 有权

    公开(公告)号：US11157409B2

    公开(公告)日：2021-10-26

    申请号：US16717868

    申请日：2019-12-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Luke Murray

    IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0891 ,  G06F12/0842

    Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.

    Synchronizing access to shared memory by extending protection for a target address of a store-conditional request
    3.
    发明授权
    Synchronizing access to shared memory by extending protection for a target address of a store-conditional request 有权

    公开(公告)号：US11106608B1

    公开(公告)日：2021-08-31

    申请号：US16908272

    申请日：2020-06-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Sanjeev Ghai

    IPC: G06F12/14 ,  G06F16/11 ,  G06F13/16 ,  G06F9/30 ,  G06F13/40 ,  G06F30/32 ,  G06F115/10

    Abstract: A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request. The cache is configured to vary a duration of the protection window extension for different snooped memory access requests based on one of broadcast scopes and the relative locations of masters of the snooped memory access requests.

    Ordering execution of an interrupt handler
    4.
    发明授权
    Ordering execution of an interrupt handler 有权

    公开(公告)号：US10831660B1

    公开(公告)日：2020-11-10

    申请号：US16455340

    申请日：2019-06-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen

    IPC: G06F12/0811 ,  G06F12/0897 ,  G06F12/12 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F12/084

    Abstract: A processing unit for a multiprocessor data processing system includes a processor core having an upper level cache and a lower level cache coupled to the processor core. The lower level cache includes one or more state machines for handling requests snooped from the system interconnect. The processing unit includes an interrupt unit configured to, based on receipt of an interrupt request while the processor core is in a powered up state, record which of the one or more state machines are active processing a prior snooped request that can invalidate a cache line in the upper level cache and present an interrupt to the processor core based on determining that each state machine that was active processing a prior snooped request that can invalidate a cache line in the upper level cache has completed processing of its respective prior snooped request.

    Translation entry invalidation in a multithreaded data processing system
    10.
    发明授权
    Translation entry invalidation in a multithreaded data processing system 有权

    公开(公告)号：US09830198B2

    公开(公告)日：2017-11-28

    申请号：US14977867

    申请日：2015-12-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Guy L. Guthrie ,  Hugh Shen ,  Derek E. Williams

    IPC: G06F9/52 ,  G06F12/0831 ,  G06F12/0808

    CPC classification number: G06F9/524 ,  G06F9/522 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/682 ,  G06F2212/683

    Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying and synchronization requests of a plurality of concurrently executing hardware threads are received in a shared queue. The plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread, and the synchronization requests includes a synchronization request of the initiating hardware thread. The translation invalidation request is broadcast such that the translation invalidation request is received and processed by the plurality of processor cores to invalidate any translation entry that translates a target address of the translation invalidation request. In response to receiving the synchronization request in the shared queue, the synchronization request is removed from the shared queue, buffered in sidecar logic, iteratively broadcast until all of the plurality of processor cores have completed processing the translation invalidation request, and thereafter removed from the sidecar logic.

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